[U-Boot] [PATCH 0/4] am57xx: beagle-x15: get usb host working

[Roger Quadros]

On 13/05/16 15:47, Marek Vasut wrote:
> On 05/13/2016 02:39 PM, Roger Quadros wrote:
>> On 13/05/16 15:17, Roger Quadros wrote:
>>> Hi,
>>>
>>> This series fixes dwc3 usb config issues and am57xx-evm USB configuration
>>> to get USB host ports working properly on am57xx-evm and beagle-x15.
>>
>> Small update. Super-Speed devices are still not working, but that is a different issue
>> which seems to have been existed since long ago. I will debug this issue in the coming days.
> 
> Cool. You have a whole MW for that ;-)

Still stuck with this issue. It seems like it finds both high-speed and
super-speed hubs but fails getting descriptor of the super-speed hub.

Is super-speed host known to work on any platform on u-boot?
Any ideas how to debug this further? The hub chip is on the board
so I can't connect a USB bus analyzer there.

cheers,
-roger

=> usb start
starting USB...
USB0:   board_usb_init 0
adding phy 0 to list
dwc3_core_soft_reset
ti_usb3_phy_power 1
usb3 power up done
dwc3_set_mode 1
config1 0x7d00e
config1 0x7d00e
config1 0x7d00e
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... USB hub found
2 ports detected
individual port power switching
standalone hub
individual port over-current protection
power on to power good time: 20ms
hub controller current requirement: 0mA
port 1 is removable
port 2 is removable
get_hub_status returned status 1, change 902
local power source is lost (inactive)
no over-current condition exists
enabling power on all ports
port 1 returns 0
port 2 returns 0
pgood_delay=20ms
devnum=1 poweron: query_delay=100 connect_timeout=1100
Port 1 Status 101 Change 1
devnum=1 port=1: USB dev found
portstatus 101, change 1, 12 Mb/s
legacy_hub_port_reset: resetting port 1...
portstatus 111, change 0, 12 Mb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
portstatus 503, change 10, 480 Mb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 1
req=6 (0x6), type=128 (0x80), value=256 (0x100), index=0
start_trb fef56940, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 256,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 18
XHCI done. status 0x0
req=6 (0x6), type=128 (0x80), value=512 (0x200), index=0
start_trb fef56970, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 512,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 9
XHCI done. status 0x0
req=6 (0x6), type=128 (0x80), value=512 (0x200), index=0
start_trb fef569a0, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 512,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 41
XHCI done. status 0x0
req=9 (0x9), type=0 (0x0), value=1 (0x1), index=0
start_trb fef569d0, start_cycle 1
req->requesttype = 0, req->request = 9,le16_to_cpu(req->value) = 1,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 0
XHCI done. status 0x0
req=6 (0x6), type=128 (0x80), value=768 (0x300), index=0
start_trb fef569f0, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 768,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 255
XHCI done. status 0x0
req=6 (0x6), type=128 (0x80), value=769 (0x301), index=1033
start_trb fef56a20, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 769,le16_to_cpu(req->index) = 1033,le16_to_cpu(req->length) = 255
XHCI done. status 0x0
USB hub found
req=6 (0x6), type=160 (0xa0), value=10496 (0x2900), index=0
start_trb fef56a50, start_cycle 1
req->requesttype = 160, req->request = 6,le16_to_cpu(req->value) = 10496,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
req=6 (0x6), type=160 (0xa0), value=10496 (0x2900), index=0
start_trb fef56a80, start_cycle 1
req->requesttype = 160, req->request = 6,le16_to_cpu(req->value) = 10496,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 9
XHCI done. status 0x0
4 ports detected
individual port power switching
standalone hub
individual port over-current protection
power on to power good time: 100ms
hub controller current requirement: 0mA
port 1 is removable
port 2 is removable
port 3 is removable
port 4 is removable
req=0 (0x0), type=160 (0xa0), value=0 (0x0), index=0
start_trb fef56ab0, start_cycle 1
req->requesttype = 160, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
get_hub_status returned status 0, change 0
local power source is good
no over-current condition exists
enabling power on all ports
req=3 (0x3), type=35 (0x23), value=8 (0x8), index=1
start_trb fef56ae0, start_cycle 1
req->requesttype = 35, req->request = 3,le16_to_cpu(req->value) = 8,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 0
XHCI done. status 0x0
port 1 returns 0
req=3 (0x3), type=35 (0x23), value=8 (0x8), index=2
start_trb fef56b00, start_cycle 1
req->requesttype = 35, req->request = 3,le16_to_cpu(req->value) = 8,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 0
XHCI done. status 0x0
port 2 returns 0
req=3 (0x3), type=35 (0x23), value=8 (0x8), index=3
start_trb fef56b20, start_cycle 1
req->requesttype = 35, req->request = 3,le16_to_cpu(req->value) = 8,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 0
XHCI done. status 0x0
port 3 returns 0
req=3 (0x3), type=35 (0x23), value=8 (0x8), index=4
start_trb fef56b40, start_cycle 1
req->requesttype = 35, req->request = 3,le16_to_cpu(req->value) = 8,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 0
XHCI done. status 0x0
port 4 returns 0
pgood_delay=100ms
devnum=2 poweron: query_delay=100 connect_timeout=1100
Port 2 Status 703 Change 1
devnum=1 port=2: USB dev found
portstatus 703, change 1, 5 Gb/s
legacy_hub_port_reset: resetting port 2...
portstatus 703, change 10, 5 Gb/s
STAT_C_CONNECTION = 0 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 1
req=6 (0x6), type=128 (0x80), value=256 (0x100), index=0
start_trb fef587c0, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 256,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 18
XHCI done. status 0x0
req=6 (0x6), type=128 (0x80), value=512 (0x200), index=0
start_trb fef587f0, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 512,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 9
XHCI done. status 0x0
req=6 (0x6), type=128 (0x80), value=512 (0x200), index=0
start_trb fef58820, start_cycle 1
req->requesttype = 128, req->request = 6,le16_to_cpu(req->value) = 512,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 31
XHCI done. status 0x0
req=9 (0x9), type=0 (0x0), value=1 (0x1), index=0
start_trb fef58850, start_cycle 1
req->requesttype = 0, req->request = 9,le16_to_cpu(req->value) = 1,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 0
XHCI done. status 0x0

*-------interesting part-------*
USB hub found
req=6 (0x6), type=160 (0xa0), value=10496 (0x2900), index=0
start_trb fef58870, start_cycle 1
req->requesttype = 160, req->request = 6,le16_to_cpu(req->value) = 10496,le16_to_cpu(req->index) = 0,le16_to_cpu(req->length) = 4
XHCI done. status 0x2
usb_hub_configure: failed to get hub descriptor, giving up 2
hub: disabling port 2
*-------end interesting part---*

req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56b60, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56b90, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56bc0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56bf0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56c20, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56c50, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56c80, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56cb0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56ce0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56d10, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56950, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56980, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef569b0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef569e0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56a10, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56a40, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56a70, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56aa0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56ad0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56b00, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56b30, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56b60, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56b90, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56bc0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56bf0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56c20, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56c50, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56c80, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56cb0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56ce0, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56d10, start_cycle 0
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56950, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56980, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef569b0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef569e0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56a10, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56a40, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56a70, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56aa0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=4
start_trb fef56ad0, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 4,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 4 Status 100 Change 0
devnum=2 port=4: timeout
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=1
start_trb fef56b00, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 1,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 1 Status 100 Change 0
devnum=2 port=1: timeout
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=2
start_trb fef56b30, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 2,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 2 Status 100 Change 0
devnum=2 port=2: timeout
req=0 (0x0), type=163 (0xa3), value=0 (0x0), index=3
start_trb fef56b60, start_cycle 1
req->requesttype = 163, req->request = 0,le16_to_cpu(req->value) = 0,le16_to_cpu(req->index) = 3,le16_to_cpu(req->length) = 4
XHCI done. status 0x0
Port 3 Status 100 Change 0
devnum=2 port=3: timeout
2 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
=>