[U-Boot] [PATCH V2 8/9] mips: ath79: Add AR934x support

[Wills Wang]

On 05/22/2016 12:49 AM, Marek Vasut wrote:
> On 05/21/2016 06:22 PM, Wills Wang wrote:
>>
>> On 05/07/2016 02:10 AM, Marek Vasut wrote:
>> [...]
>>> +
>>> +static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32
>>> srif_val)
>>> +{
>>> +    u32 reg;
>>> +    do {
>>> +        writel(0x10810f00, pll_reg_base + 0x4);
>>> +        writel(srif_val, pll_reg_base + 0x0);
>>> +        writel(0xd0810f00, pll_reg_base + 0x4);
>>> +        writel(0x03000000, pll_reg_base + 0x8);
>>> +        writel(0xd0800f00, pll_reg_base + 0x4);
>>> +
>>> +        clrbits_be32(pll_reg_base + 0x8, BIT(30));
>>> +        udelay(5);
>>> +        setbits_be32(pll_reg_base + 0x8, BIT(30));
>>> +        udelay(5);
>>> +
>>> +        wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
>>> +
>>> +        clrbits_be32(pll_reg_base + 0x8, BIT(30));
>>> +        udelay(5);
>>> +
>>> +        /* Check if CPU SRIF PLL locked. */
>>> +        reg = readl(pll_reg_base + 0x8);
>>> +        reg = (reg & 0x7ffff8) >> 3;
>>> +    } while (reg >= 0x40000);
>>> +}
>>> +
>>> +void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16
>>> ahb_mhz)
>>> +{
>> Is it possible to addthe uniform entry for platform PLL initialization,
>> such as "pll_init"?
> Yes, this should happen at some point.
>
>> [...]
>> +
>> +static void ar934x_update_clock(void)
>> +{
>> +    void __iomem *regs;
>> +    u32 ctrl, cpu, cpupll, ddr, ddrpll;
>> +    u32 cpudiv, ddrdiv, busdiv;
>> +    u32 cpuclk, ddrclk, busclk;
>> +
>> +    regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>> +               MAP_NOCACHE);
>> +
>> +    cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
>> +    ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
>> +    ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
>> +
>> +    cpupll = ar934x_cpupll_to_hz(cpu);
>> +    ddrpll = ar934x_ddrpll_to_hz(ddr);
>> +
>> +    if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
>> +        cpuclk = ar934x_get_xtal();
>> +    else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
>> +        cpuclk = cpupll;
>> +    else
>> +        cpuclk = ddrpll;
>> +
>> +    if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
>> +        ddrclk = ar934x_get_xtal();
>> +    else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
>> +        ddrclk = ddrpll;
>> +    else
>> +        ddrclk = cpupll;
>> +
>> +    if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
>> +        busclk = ar934x_get_xtal();
>> +    else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
>> +        busclk = ddrpll;
>> +    else
>> +        busclk = cpupll;
>> +
>> +    cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
>> +         AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
>> +    ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
>> +         AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
>> +    busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
>> +         AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
>> +
>> +    gd->cpu_clk = cpuclk / (cpudiv + 1);
>> +    gd->mem_clk = ddrclk / (ddrdiv + 1);
>> +    gd->bus_clk = busclk / (busdiv + 1);
>> +}
>> +
>> +ulong get_bus_freq(ulong dummy)
>> +{
>> +    ar934x_update_clock();
>>
>> Here i think clock need not be update on each call.
>>> +    return gd->bus_clk;
>>> +}
>>> +
>>> +ulong get_ddr_freq(ulong dummy)
>>> +{
>>> +    ar934x_update_clock();
>> Same as above.
>>> +    return gd->mem_clk;
>>> +}
>>> +
>>> +int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char *
>>> const argv[])
>>> +{
>>> +    ar934x_update_clock();
>> Same as above.
>>
>> [...]
>> +
>> +static const struct ar934x_mem_config ar934x_mem_config[] = {
>> +    [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
>> +    [AR934X_DDR1]  = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
>> +    [AR934X_DDR2]  = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
>> +};
>> +
>> +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16
>> ahb_mhz)
>> +{
>>
>> Is it possible to use the uniform entry "ddr_init" for DDR initialization?
> No, it doesn't allow the board to specify the per-board parameters.
>
In ar934x_ddr_init, these parameters was never used.
>>> +    void __iomem *ddr_regs;
>>> +    const struct ar934x_mem_config *memcfg;
>>> +    int memtype;
>>> +    u32 reg, cycle, ctl;
>>> +
>>> +    ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
>>> +                   MAP_NOCACHE);
>>> +
>> [...]
>>> diff --git a/arch/mips/mach-ath79/include/mach/ath79.h
>>> b/arch/mips/mach-ath79/include/mach/ath79.h
>>> index 2c6c118..17af082 100644
>>> --- a/arch/mips/mach-ath79/include/mach/ath79.h
>>> +++ b/arch/mips/mach-ath79/include/mach/ath79.h
>>> @@ -143,4 +143,7 @@ static inline int soc_is_qca956x(void)
>>>    int ath79_eth_reset(void);
>>>    int ath79_usb_reset(void);
>>>    +void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const
>>> u16 ahb_mhz);
>> I think if we can add a common header for a consistent interface for
>> platform clock initialization,
>> such as "clk.h".
>>> +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16
>>> ahb_mhz);
>>> +
>> I think it should be moved into mach/ddr.h.
> Sure, further patches are welcome.
>
>>>    #endif /* __ASM_MACH_ATH79_H */
>

-- 
Best Regards
Wills