[U-Boot] [PATCH v3 1/5] gpio: atmel_pio4: Move PIO4 definitions to head file

Wenyou Yang wenyou.yang at atmel.com
Thu May 26 06:21:40 CEST 2016


In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.

Signed-off-by: Wenyou Yang <wenyou.yang at atmel.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm/mach-at91/include/mach/atmel_pio4.h | 35 ++++++++++++++
 drivers/gpio/atmel_pio4.c                    | 71 +++++++---------------------
 2 files changed, 53 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h
index 8bb4b12..6760bec 100644
--- a/arch/arm/mach-at91/include/mach/atmel_pio4.h
+++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h
@@ -29,6 +29,41 @@ struct atmel_pio4_port {
 
 #endif
 
+/*
+ * PIO Configuration Register Fields
+ */
+#define ATMEL_PIO_CFGR_FUNC_MASK	GENMASK(2, 0)
+#define ATMEL_PIO_CFGR_FUNC_GPIO	(0x0 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_A	(0x1 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_B	(0x2 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_C	(0x3 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_D	(0x4 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_E	(0x5 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_F	(0x6 << 0)
+#define ATMEL_PIO_CFGR_FUNC_PERIPH_G	(0x7 << 0)
+#define ATMEL_PIO_DIR_MASK		BIT(8)
+#define ATMEL_PIO_PUEN_MASK		BIT(9)
+#define ATMEL_PIO_PDEN_MASK		BIT(10)
+#define ATMEL_PIO_IFEN_MASK		BIT(12)
+#define ATMEL_PIO_IFSCEN_MASK		BIT(13)
+#define ATMEL_PIO_OPD_MASK		BIT(14)
+#define ATMEL_PIO_SCHMITT_MASK		BIT(15)
+#define ATMEL_PIO_CFGR_EVTSEL_MASK	GENMASK(26, 24)
+#define ATMEL_PIO_CFGR_EVTSEL_FALLING	(0 << 24)
+#define ATMEL_PIO_CFGR_EVTSEL_RISING	(1 << 24)
+#define ATMEL_PIO_CFGR_EVTSEL_BOTH	(2 << 24)
+#define ATMEL_PIO_CFGR_EVTSEL_LOW	(3 << 24)
+#define ATMEL_PIO_CFGR_EVTSEL_HIGH	(4 << 24)
+
+#define ATMEL_PIO_NPINS_PER_BANK	32
+#define ATMEL_PIO_BANK(pin_id)		(pin_id / ATMEL_PIO_NPINS_PER_BANK)
+#define ATMEL_PIO_LINE(pin_id)		(pin_id % ATMEL_PIO_NPINS_PER_BANK)
+#define ATMEL_PIO_BANK_OFFSET		0x40
+
+#define ATMEL_GET_PIN_NO(pinfunc)	((pinfunc) & 0xff)
+#define ATMEL_GET_PIN_FUNC(pinfunc)	((pinfunc >> 16) & 0xf)
+#define ATMEL_GET_PIN_IOSET(pinfunc)	((pinfunc >> 20) & 0xf)
+
 #define AT91_PIO_PORTA		0x0
 #define AT91_PIO_PORTB		0x1
 #define AT91_PIO_PORTC		0x2
diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
index d71f525..84e8cc5 100644
--- a/drivers/gpio/atmel_pio4.c
+++ b/drivers/gpio/atmel_pio4.c
@@ -12,41 +12,6 @@
 #include <mach/gpio.h>
 #include <mach/atmel_pio4.h>
 
-#define ATMEL_PIO4_PINS_PER_BANK	32
-
-/*
- * Register Field Definitions
- */
-#define ATMEL_PIO4_CFGR_FUNC	(0x7 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_GPIO	(0x0 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_A	(0x1 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_B	(0x2 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_C	(0x3 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_D	(0x4 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_E	(0x5 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_F	(0x6 << 0)
-#define		ATMEL_PIO4_CFGR_FUNC_PERIPH_G	(0x7 << 0)
-#define ATMEL_PIO4_CFGR_DIR	(0x1 << 8)
-#define ATMEL_PIO4_CFGR_PUEN	(0x1 << 9)
-#define ATMEL_PIO4_CFGR_PDEN	(0x1 << 10)
-#define ATMEL_PIO4_CFGR_IFEN	(0x1 << 12)
-#define ATMEL_PIO4_CFGR_IFSCEN	(0x1 << 13)
-#define ATMEL_PIO4_CFGR_OPD	(0x1 << 14)
-#define ATMEL_PIO4_CFGR_SCHMITT	(0x1 << 15)
-#define ATMEL_PIO4_CFGR_DRVSTR	(0x3 << 16)
-#define		ATMEL_PIO4_CFGR_DRVSTR_LOW0	(0x0 << 16)
-#define		ATMEL_PIO4_CFGR_DRVSTR_LOW1	(0x1 << 16)
-#define		ATMEL_PIO4_CFGR_DRVSTR_MEDIUM	(0x2 << 16)
-#define		ATMEL_PIO4_CFGR_DRVSTR_HIGH	(0x3 << 16)
-#define ATMEL_PIO4_CFGR_EVTSEL	(0x7 << 24)
-#define		ATMEL_PIO4_CFGR_EVTSEL_FALLING	(0x0 << 24)
-#define		ATMEL_PIO4_CFGR_EVTSEL_RISING	(0x1 << 24)
-#define		ATMEL_PIO4_CFGR_EVTSEL_BOTH	(0x2 << 24)
-#define		ATMEL_PIO4_CFGR_EVTSEL_LOW	(0x3 << 24)
-#define		ATMEL_PIO4_CFGR_EVTSEL_HIGH	(0x4 << 24)
-#define ATMEL_PIO4_CFGR_PCFS	(0x1 << 29)
-#define ATMEL_PIO4_CFGR_ICFS	(0x1 << 30)
-
 static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
 {
 	struct atmel_pio4_port *base = NULL;
@@ -79,7 +44,7 @@ static int atmel_pio4_config_io_func(u32 port, u32 pin,
 	struct atmel_pio4_port *port_base;
 	u32 reg, mask;
 
-	if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+	if (pin >= ATMEL_PIO_NPINS_PER_BANK)
 		return -ENODEV;
 
 	port_base = atmel_pio4_port_base(port);
@@ -88,7 +53,7 @@ static int atmel_pio4_config_io_func(u32 port, u32 pin,
 
 	mask = 1 << pin;
 	reg = func;
-	reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0;
+	reg |= use_pullup ? ATMEL_PIO_PUEN_MASK : 0;
 
 	writel(mask, &port_base->mskr);
 	writel(reg, &port_base->cfgr);
@@ -99,56 +64,56 @@ static int atmel_pio4_config_io_func(u32 port, u32 pin,
 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_GPIO,
+					 ATMEL_PIO_CFGR_FUNC_GPIO,
 					 use_pullup);
 }
 
 int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_A,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
 					 use_pullup);
 }
 
 int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_B,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
 					 use_pullup);
 }
 
 int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_C,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
 					 use_pullup);
 }
 
 int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_D,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
 					 use_pullup);
 }
 
 int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_E,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
 					 use_pullup);
 }
 
 int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_F,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
 					 use_pullup);
 }
 
 int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
 {
 	return atmel_pio4_config_io_func(port, pin,
-					 ATMEL_PIO4_CFGR_FUNC_PERIPH_G,
+					 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
 					 use_pullup);
 }
 
@@ -157,7 +122,7 @@ int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
 	struct atmel_pio4_port *port_base;
 	u32 reg, mask;
 
-	if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+	if (pin >= ATMEL_PIO_NPINS_PER_BANK)
 		return -ENODEV;
 
 	port_base = atmel_pio4_port_base(port);
@@ -165,7 +130,7 @@ int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
 		return -ENODEV;
 
 	mask = 0x01 << pin;
-	reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
+	reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
 
 	writel(mask, &port_base->mskr);
 	writel(reg, &port_base->cfgr);
@@ -183,7 +148,7 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin)
 	struct atmel_pio4_port *port_base;
 	u32 reg, mask;
 
-	if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+	if (pin >= ATMEL_PIO_NPINS_PER_BANK)
 		return -ENODEV;
 
 	port_base = atmel_pio4_port_base(port);
@@ -191,7 +156,7 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin)
 		return -ENODEV;
 
 	mask = 0x01 << pin;
-	reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
+	reg = ATMEL_PIO_CFGR_FUNC_GPIO;
 
 	writel(mask, &port_base->mskr);
 	writel(reg, &port_base->cfgr);
@@ -205,7 +170,7 @@ static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
 	struct at91_port_platdata *plat = dev_get_platdata(dev);
 	struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
 	u32 mask = 0x01 << offset;
-	u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
+	u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
 
 	writel(mask, &port_base->mskr);
 	writel(reg, &port_base->cfgr);
@@ -219,7 +184,7 @@ static int atmel_pio4_direction_output(struct udevice *dev,
 	struct at91_port_platdata *plat = dev_get_platdata(dev);
 	struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
 	u32 mask = 0x01 << offset;
-	u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
+	u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
 
 	writel(mask, &port_base->mskr);
 	writel(reg, &port_base->cfgr);
@@ -265,7 +230,7 @@ static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
 	writel(mask, &port_base->mskr);
 
 	return (readl(&port_base->cfgr) &
-		ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT;
+		ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 
 static const struct dm_gpio_ops atmel_pio4_ops = {
@@ -282,7 +247,7 @@ static int atmel_pio4_probe(struct udevice *dev)
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
 	uc_priv->bank_name = plat->bank_name;
-	uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK;
+	uc_priv->gpio_count = ATMEL_PIO_NPINS_PER_BANK;
 
 	return 0;
 }
-- 
2.7.4



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