[U-Boot] [PATCH 2/3] MIPS: Split I & D cache line size config

[Daniel Schwierzeck]

Am 26.05.2016 um 17:58 schrieb Paul Burton:
> Allow L1 Icache & L1 Dcache line size to be specified separately, since
> there's no architectural mandate that they be the same. The
> [id]cache_line_size functions are tidied up to take advantage of the
> fact that the Kconfig entries are always present to simply check them
> for zero rather than needing to #ifdef on their presence.
> 
> Signed-off-by: Paul Burton <paul.burton at imgtec.com>
> ---
> 
>  arch/mips/Kconfig            |  6 +++++-
>  arch/mips/lib/cache.c        | 22 +++++++---------------
>  arch/mips/lib/cache_init.S   |  4 ++--
>  board/dbau1x00/Kconfig       |  5 ++++-
>  board/micronas/vct/Kconfig   |  5 ++++-
>  board/pb1x00/Kconfig         |  5 ++++-
>  board/qca/ap121/Kconfig      |  5 ++++-
>  board/qca/ap143/Kconfig      |  5 ++++-
>  board/qemu-mips/Kconfig      |  5 ++++-
>  board/tplink/wdr4300/Kconfig |  5 ++++-
>  10 files changed, 42 insertions(+), 25 deletions(-)
> 

applied to u-boot-mips, thanks!

-- 
- Daniel

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