[U-Boot] [PATCH v2 2/3] MIPS: Split I & D cache line size config

[Daniel Schwierzeck]

Am 27.05.2016 um 15:28 schrieb Paul Burton:
> Allow L1 Icache & L1 Dcache line size to be specified separately, since
> there's no architectural mandate that they be the same. The
> [id]cache_line_size functions are tidied up to take advantage of the
> fact that the Kconfig entries are always present to simply check them
> for zero rather than needing to #ifdef on their presence.
> 
> Signed-off-by: Paul Burton <paul.burton at imgtec.com>
> 
> ---
> 
> Changes in v2:
> - Provide CONFIG_SYS_CACHELINE_SIZE as a synonym for ARCH_DMA_MINALIGN to avoid breaking drivers that use it for now.
> 
>  arch/mips/Kconfig             | 12 +++++++++---
>  arch/mips/include/asm/cache.h |  7 +++++++
>  arch/mips/lib/cache.c         | 22 +++++++---------------
>  arch/mips/lib/cache_init.S    |  4 ++--
>  board/dbau1x00/Kconfig        |  5 ++++-
>  board/micronas/vct/Kconfig    |  5 ++++-
>  board/pb1x00/Kconfig          |  5 ++++-
>  board/qca/ap121/Kconfig       |  5 ++++-
>  board/qca/ap143/Kconfig       |  5 ++++-
>  board/qemu-mips/Kconfig       |  5 ++++-
>  board/tplink/wdr4300/Kconfig  |  5 ++++-
>  11 files changed, 53 insertions(+), 27 deletions(-)
> 

applied to u-boot-mips, thanks!

-- 
- Daniel

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