[U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x

[Wills Wang]

On 05/31/2016 04:50 PM, Piotr Dymacz wrote:
> Hello,
>
> 2016-05-31 2:51 GMT+02:00 Marek Vasut <marex at denx.de>:
>> On 05/31/2016 02:35 AM, Wills Wang wrote:
> [snip]
>
>>>>>    +static int usb_reset_qca953x(void __iomem *reset_regs)
>>>>> +{
>>>>> +    void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>>>>> +                      MAP_NOCACHE);
>>>>> +
>>>>> +    clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>>>>> +            0xf00, 0x200);
>> Do you know what these magic numbers mean ?
> I can help here.
>
> This register is common for (almost) all modern QC/A WiSOCs, with
> similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
> (please take a look at [1]).
> I have seen it (SDK, datasheets) under two different names:
> SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
> (offset +/- 1), depending on the SOC.
>
> The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
> all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.
You are right, i found the same description in ar9341 data sheet.
> I'm going to provide some patches for ath79 in future, which will make
> code more universal for all QC/A WiSOCs.
You are always welcome.
> --
> Regards,
> Piotr Dymacz
>
> [1] http://postimg.org/image/tyrkhkw57/full/
>
>>>>> +    mdelay(10);
>>>>> +
>>>>> +    /* Ungate the USB block */
>>>>> +    setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> +             QCA953X_RESET_USBSUS_OVERRIDE);
>>>>> +    mdelay(1);
>>>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> +             QCA953X_RESET_USB_PHY);
>>>>> +    mdelay(1);
>>>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> +             QCA953X_RESET_USB_PHY_ANALOG);
>>>>> +    mdelay(1);
>>>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> +             QCA953X_RESET_USB_HOST);
>>>>> +    mdelay(1);
>>>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> +             QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
>>>>> +    mdelay(1);
>>>>> +
>>>>> +    return 0;
>>>>> +}
>>>>> +
>>>>>    int ath79_usb_reset(void)
>>>>>    {
>>>>>        void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
>>>>> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
>>>>>            return usb_reset_ar933x(reset_regs);
>>>>>        if (soc_is_ar934x())
>>>>>            return usb_reset_ar934x(reset_regs);
>>>>> +    if (soc_is_qca953x())
>>>>> +        return usb_reset_qca953x(reset_regs);
>>>>>          return -EINVAL;
>>>>>    }
>>>>>
>>
>> --
>> Best regards,
>> Marek Vasut
>> _______________________________________________
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>> U-Boot at lists.denx.de
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-- 
Best Regards
Wills