[U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization

[york sun]

On 10/12/2016 05:15 AM, Pratiyush Srivastava wrote:
> Clear the content to zero and the ECC error bit of OCRAM1/2.
>
> The OCRAM must be initialized to ZERO by the unit of 8-Byte before
> accessing it, or else it will generate ECC error. And the IBR has
> accessed the OCRAM before this initialization, so the ECC error
> status bit should to be cleared.

Does the ECC error trigger any exception? Why didn't we see the error 
before?

>
> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava at nxp.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
> ---
>  arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
> index 19c771d..24fed46 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -11,6 +11,9 @@
>  #include <asm/macro.h>
>  #include <asm/armv8/mmu.h>
>
> +#define DCSR_SYS_DCFG_SBEESR2	0x20140534
> +#define DCSR_SYS_DCFG_MBEESR2	0x20140544
> +
>  /*************************************************************************
>   *
>   * Startup Code (reset vector)
> @@ -259,10 +262,46 @@ WEAK(lowlevel_init)
>  #endif /* CONFIG_ARMV8_MULTIENTRY */
>
>  2:
> +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
> +	bl	fsl_ocram_init
> +#endif

Why do you change this weak function, not the one in lowerlevel.S?

York