[U-Boot] [PATCH 3/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Mugunthan V N]

On Thursday 13 October 2016 09:39 AM, Lokesh Vutla wrote:
> 
> 
> On Monday 10 October 2016 06:27 PM, Mugunthan V N wrote:
>> cpsw driver supports only selection of phy mode in control module
>> but control module has more setting like RGMII ID mode selection,
>> RMII clock source selection. So ported to cpsw-phy-sel driver
>> from kernel to u-boot.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm at ti.com>
>> ---
>>  drivers/net/cpsw.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++++-----
>>  include/cpsw.h     |   1 +
>>  2 files changed, 140 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
>> index d17505e..1441f44 100644
>> --- a/drivers/net/cpsw.c
>> +++ b/drivers/net/cpsw.c
>> @@ -225,6 +225,18 @@ struct cpdma_chan {
>>  	void			*hdp, *cp, *rxfree;
>>  };
>>  
>> +/* AM33xx SoC specific definitions for the CONTROL port */
>> +#define AM33XX_GMII_SEL_MODE_MII	0
>> +#define AM33XX_GMII_SEL_MODE_RMII	1
>> +#define AM33XX_GMII_SEL_MODE_RGMII	2
>> +
>> +#define AM33XX_GMII_SEL_RGMII1_IDMODE	BIT(4)
>> +#define AM33XX_GMII_SEL_RGMII2_IDMODE	BIT(5)
>> +#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN	BIT(6)
>> +#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN	BIT(7)
>> +
>> +#define GMII_SEL_MODE_MASK		0x3
>> +
>>  #define desc_write(desc, fld, val)	__raw_writel((u32)(val), &(desc)->fld)
>>  #define desc_read(desc, fld)		__raw_readl(&(desc)->fld)
>>  #define desc_read_ptr(desc, fld)	((void *)__raw_readl(&(desc)->fld))
>> @@ -1150,12 +1162,129 @@ static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
>>  						  false);
>>  }
>>  
>> +static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
>> +				 phy_interface_t phy_mode)
>> +{
>> +	u32 reg;
>> +	u32 mask;
>> +	u32 mode = 0;
>> +	bool rgmii_id = false;
>> +	int slave = priv->data.active_slave;
>> +
>> +	reg = readl(priv->data.gmii_sel);
>> +
>> +	switch (phy_mode) {
>> +	case PHY_INTERFACE_MODE_RMII:
>> +		mode = AM33XX_GMII_SEL_MODE_RMII;
>> +		break;
>> +
>> +	case PHY_INTERFACE_MODE_RGMII:
>> +		mode = AM33XX_GMII_SEL_MODE_RGMII;
>> +		break;
>> +	case PHY_INTERFACE_MODE_RGMII_ID:
>> +	case PHY_INTERFACE_MODE_RGMII_RXID:
>> +	case PHY_INTERFACE_MODE_RGMII_TXID:
>> +		mode = AM33XX_GMII_SEL_MODE_RGMII;
>> +		rgmii_id = true;
>> +		break;
>> +
>> +	case PHY_INTERFACE_MODE_MII:
>> +	default:
>> +		mode = AM33XX_GMII_SEL_MODE_MII;
>> +		break;
>> +	};
>> +
>> +	mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
>> +	mode <<= slave * 2;
>> +
>> +	if (priv->data.rmii_clock_external) {
> 
> I do not see any one updating value for priv->data.rmii_clock_external.
> I guess cpsw_eth_ofdata_to_platdata() should be populating this value
> based on DT.
> 

Oops, missed squashing fixup patches from TI repo. Will be careful next
time. Thanks for pointing out early.

Regards
Mugunthan V N