[U-Boot] [PATCH v3 04/12] arm: socfpga: clkmgr: Separate the Clock Manager for Stratix 10

[Chin Liang See]

Separate the Clock Manager to support both GEN5 SoC and
Stratix 10 SoC.

Signed-off-by: Chin Liang See <clsee at altera.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
Cc: Ley Foon Tan <lftan at altera.com>
Cc: Tien Fong Chee <tfchee at altera.com>
---
 arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..0d67b3c 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,6 +10,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static const struct socfpga_clock_manager *clock_manager_base =
 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
@@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
 	return clock;
 }
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 
 unsigned int cm_get_mmc_controller_clk_hz(void)
 {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	uint32_t reg, clock = 0;
 
 	/* identify the source of MMC clock */
@@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
 	/* further divide by 4 as we have fixed divider at wrapper */
 	clock /= 4;
 	return clock;
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	return 25000000;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
 }
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
 	uint32_t reg, clock = 0;
@@ -556,3 +563,4 @@ U_BOOT_CMD(
 	"display clocks",
 	""
 );
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
-- 
2.2.2