[U-Boot] CPU up timeout. CPU up mask is 1 should be 3

Wesolowski, Carol carol.wesolowski at kollmorgen.com
Thu Oct 13 01:27:18 CEST 2016


Hello,

I'm using u-boot.bin built from u-boot-2009.11-cloud.   I have single core boards that run this same u-boot.bin but I don't see the "CPU up timeout." message in the u-boot start up screen.

//dual core u-boot
U-Boot 2009.11 (Oct 10 2016 - 19:17:09)

CPU0:  P2020, Version: 2.1, (0x80e20021)
Core:  E500, Version: 5.1, (0x80211051)
Clock Configuration:
       CPU0:1200 MHz, CPU1:1200 MHz,
       CCB:600  MHz,
       DDR:400  MHz (800 MT/s data rate) (Asynchronous), LBC:75   MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
PCMM: P2020
I2C:   ready
SPI:   ready
DRAM:  Configuring DDR for 800 MT/s data rate
DDR: 256 MB
FLASH: 64 MB
L2:    512 KB enabled
CPU up timeout. CPU up mask is 1 should be 3
MMC:  FSL_ESDHC: 0
EEPROM: Invalid ID (4b 41 53 00)
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1: No support for PHY id 221560; assuming generic
eTSEC2: No support for PHY id ffffffff; assuming generic
eTSEC3: No support for PHY id 221560; assuming generic
eTSEC1, eTSEC2, eTSEC3
Hit any key to stop autoboot:  0

//single core u-boot
U-Boot 2009.11 (Apr 12 2013 - 09:40:13)

CPU:   P2010, Version: 2.1, (0x80e30021)
Core:  E500, Version: 5.1, (0x80211051)
Clock Configuration:
       CPU0:1200 MHz,
       CCB:600  MHz,
       DDR:400  MHz (800 MT/s data rate) (Asynchronous), LBC:75   MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
PCMM: P2010
I2C:   ready
SPI:   ready
DRAM:  Configuring DDR for 800 MT/s data rate
DDR: 256 MB
FLASH: 64 MB
L2:    512 KB enabled
MMC:  FSL_ESDHC: 0
*** Warning - bad CRC, using default environment

EEPROM: Invalid ID (ff ff ff ff)
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1: No support for PHY id 221556; assuming generic
eTSEC2: No support for PHY id ffffffff; assuming generic
eTSEC3: No support for PHY id 221556; assuming generic
eTSEC1, eTSEC2, eTSEC3
Hit any key to stop autoboot:  0


Do I need to modify something in my u-boot code to enable the second core?

~Thanks, Carol

Carol Wesolowski
Software Engineer
Kollmorgen
33 South La Patera Lane
Santa Barbara, CA 93117
T:  +1.805.696.1248
carol.wesolowski at Kollmorgen.com<mailto:carol.wesolowski at Kollmorgen.com>
www.Kollmorgen.com<http://www.kollmorgen.com/>

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