[U-Boot] [PATCH v3 11/12] arm: socfpga: Add SPL support for Stratix 10 SoC

[Chin Liang See]

On Min, 2016-10-16 at 17:41 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > 
> > Add SPL support for Stratix 10 SoC development kit
> > 
> > Signed-off-by: Chin Liang See <clsee at altera.com>
> > Cc: Marek Vasut <marex at denx.de>
> > Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
> > Cc: Ley Foon Tan <lftan at altera.com>
> > Cc: Tien Fong Chee <tfchee at altera.com>
> > ---
> >  arch/arm/mach-socfpga/Makefile | 13 ++++++++-----
> >  arch/arm/mach-socfpga/spl.c    | 13 ++++++++++++-
> >  2 files changed, 20 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 5038919..2b00c8c 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -8,17 +8,20 @@
> >  #
> > 
> >  obj-y        += misc.o timer.o reset_manager.o clock_manager.o
> > board.o
> > -
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > -
> >  obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += mmu-arm64.o
> > 
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
> > +endif
> > +
> > +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> >  # QTS-generated config file wrappers
> > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5)    += scan_manager.o
> > wrap_pll_config.o \
> > -                                        fpga_manager.o
> > system_manager.o
> > +obj-y        += scan_manager.o wrap_pll_config.o fpga_manager.o
> > system_manager.o
> >  obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o
> > wrap_pinmux_config.o  \
> >                          wrap_sdram_config.o
> >  CFLAGS_wrap_iocsr_config.o   += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pinmux_config.o  += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_pll_config.o     += -I$(srctree)/board/$(BOARDDIR)
> >  CFLAGS_wrap_sdram_config.o   += -I$(srctree)/board/$(BOARDDIR)
> > +endif
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index fec4c7a..b514a01 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> It seems like the only thing which happens in the spl.c for S10 is it
> calls spl_console_init(). In that case, just split the spl into gen5
> one
> and S10 one instead of polluting it with ifdefs.
> 

Ok can split this out as already seeing different flow for S10
hardware.

Thanks
Chin Liang