[U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942

[Hamish Martin]

This erratum is already implemented for other ARM based QorIQ
platforms with the Gen4 DDR controller. Port the fix to the Gen3
controller and enable it for T2080 and T2081.

Reviewed-by: Chris Packham <chris.packham at alliedtelesis.co.nz>
Signed-off-by: Hamish Martin <hamish.martin at alliedtelesis.co.nz>
Cc: York Sun <york.sun at nxp.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |  3 +++
 arch/powerpc/include/asm/config_mpc85xx.h |  1 +
 drivers/ddr/fsl/mpc85xx_ddr_gen3.c        | 17 +++++++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3b06ae42e4bc..94b6dcca96b6 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -329,6 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 	puts("Work-around for Erratum A009663 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+	puts("Work-around for Erratum A009942 enabled\n");
+#endif
 
 	return 0;
 }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e859f4a..9e1cd80e16e0 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 653b7f0c770c..a88884377f80 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -39,6 +39,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 	u32 save1, save2;
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+	ulong ddr_freq;
+	u32 tmp;
+#endif
 
 	switch (ctrl_num) {
 	case 0:
@@ -183,6 +187,19 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->debug[21], 0x24000000);
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	tmp = in_be32(&ddr->debug[28]);
+	if (ddr_freq <= 1333)
+		out_be32(&ddr->debug[28], tmp | 0x0080006a);
+	else if (ddr_freq <= 1600)
+		out_be32(&ddr->debug[28], tmp | 0x0070006f);
+	else if (ddr_freq <= 1867)
+		out_be32(&ddr->debug[28], tmp | 0x00700076);
+	else if (ddr_freq <= 2133)
+		out_be32(&ddr->debug[28], tmp | 0x0060007b);
+#endif
+
 	/*
 	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 	 * deasserted. Clocks start when any chip select is enabled and clock
-- 
2.10.1