[U-Boot] [PATCH] net: add synopsys QoS ethernet driver
Nathan Sullivan
nathan.sullivan at ni.com
Tue Oct 18 18:35:58 CEST 2016
This NIC is similar to the designware nic, however it has different
registers and descriptors, hence the new driver.
Signed-off-by: Nathan Sullivan <nathan.sullivan at ni.com>
---
drivers/net/Kconfig | 19 ++
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 773 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/dwc_eth_qos.h | 219 +++++++++++++
4 files changed, 1012 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos.c
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 302c005..7a4dc68 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -124,6 +124,25 @@ config ETH_DESIGNWARE
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
+config ETH_DESIGNWARE_QOS
+ bool "Synopsys Designware Ethernet QoS MAC"
+ select PHYLIB
+ help
+ This MAC is present in SoCs from various vendors. It supports
+ 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
+ provide the PHY (physical media interface). It is similar to
+ designware ethernet, but with more features and a different
+ interface.
+
+config ETH_DESIGNWARE_QOS_FIXED_LINK
+ bool "Fixed 1G link on QoS MAC"
+ default n
+ depends on ETH_DESIGNWARE_QOS
+ help
+ Select to force the QoS MAC to always link at 1G, full duplex
+ with no attached phy. Useful for direct attachment to a
+ switch.
+
config ETHOC
bool "OpenCores 10/100 Mbps Ethernet MAC"
help
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a448526..c8ba347 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
+obj-$(CONFIG_ETH_DESIGNWARE_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DNET) += dnet.o
obj-$(CONFIG_E1000) += e1000.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
new file mode 100644
index 0000000..f97fca1
--- /dev/null
+++ b/drivers/net/dwc_eth_qos.c
@@ -0,0 +1,773 @@
+/*
+ * (C) Copyright 2016
+ * National Instruments
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Designware QoS ethernet IP driver for U-Boot
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <pci.h>
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include "dwc_eth_qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK
+
+static int dw_qos_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+#ifdef CONFIG_DM_ETH
+ struct dw_qos_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
+ struct eth_mac_regs *mac_p = bus->priv;
+#endif
+ ulong start;
+ u32 miiaddr;
+ int timeout = CONFIG_MDIO_TIMEOUT;
+
+ miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+ ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_READ;
+
+ miiaddr |= (MII_CLKRANGE_150_250M << MIICLKSHIFT) & MII_CLKMSK;
+
+ writel(miiaddr | MII_BUSY, &mac_p->miiaddr);
+
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ if (!(readl(&mac_p->miiaddr) & MII_BUSY))
+ return readl(&mac_p->miidata);
+ udelay(10);
+ };
+
+ return -ETIMEDOUT;
+}
+
+static int dw_qos_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+#ifdef CONFIG_DM_ETH
+ struct dw_qos_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
+ struct eth_mac_regs *mac_p = bus->priv;
+#endif
+ ulong start;
+ u32 miiaddr;
+ int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
+
+ writel(val, &mac_p->miidata);
+ miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+ ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
+
+ miiaddr |= (MII_CLKRANGE_150_250M << MIICLKSHIFT) & MII_CLKMSK;
+
+ writel(miiaddr | MII_BUSY, &mac_p->miiaddr);
+
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ };
+
+ return ret;
+}
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
+static int dw_qos_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+ struct dw_qos_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return 0;
+
+ /* reset the phy */
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[0]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[1]);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret)
+ return ret;
+
+ udelay(pdata->reset_delays[2]);
+
+ return 0;
+}
+#endif
+
+static int dw_qos_mdio_init(const char *name, void *priv)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = dw_qos_mdio_read;
+ bus->write = dw_qos_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
+ bus->reset = dw_qos_mdio_reset;
+#endif
+
+ bus->priv = priv;
+
+ return mdio_register(bus);
+}
+
+static void dw_qos_adjust_link(struct eth_mac_regs *mac_p,
+ struct phy_device *phydev)
+{
+ u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
+
+ if (!phydev->link) {
+ printf("%s: No link.\n", phydev->dev->name);
+ return;
+ }
+
+ if (phydev->speed != 1000)
+ conf |= MII_PORTSELECT;
+ else
+ conf &= ~MII_PORTSELECT;
+
+ if (phydev->speed == 100)
+ conf |= FES_100;
+
+ if (phydev->duplex)
+ conf |= FULLDPLXMODE;
+
+ writel(conf, &mac_p->conf);
+
+ printf("Speed: %d, %s duplex%s\n", phydev->speed,
+ (phydev->duplex) ? "full" : "half",
+ (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
+}
+
+static int dw_qos_phy_init(struct dw_qos_eth_dev *priv, void *dev)
+{
+ struct phy_device *phydev;
+ int mask = 0xffffffff, ret;
+
+#ifdef CONFIG_PHY_ADDR
+ mask = 1 << CONFIG_PHY_ADDR;
+#endif
+
+ phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ if (!phydev)
+ return -ENODEV;
+
+ phy_connect_dev(phydev, dev);
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->max_speed) {
+ ret = phy_set_supported(phydev, priv->max_speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+#endif /* CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK */
+
+static void tx_descs_init(struct dw_qos_eth_dev *priv)
+{
+ struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p;
+ struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
+ char *txbuffs = &priv->txbuffs[0];
+ struct dmamacdescr *desc_p;
+ u32 idx;
+
+ for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+ desc_p = &desc_table_p[idx];
+ desc_p->des0 = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->des1 = 0;
+ desc_p->des2 = 0;
+ desc_p->des3 = DESC_TXSTS_TXLAST | DESC_TXSTS_TXFIRST;
+ }
+
+ /* Flush all Tx buffer descriptors at once */
+ flush_dcache_range((ulong)priv->tx_mac_descrtable,
+ (ulong)priv->tx_mac_descrtable +
+ sizeof(priv->tx_mac_descrtable));
+
+ writel(0, &ch0_p->txdescaddrhi);
+ writel((ulong)&desc_table_p[0], &ch0_p->txdescaddrlo);
+ writel(CONFIG_TX_DESCR_NUM - 1, &ch0_p->txdescringlen);
+ writel((ulong)&desc_table_p[CONFIG_TX_DESCR_NUM], &ch0_p->txdesctail);
+ priv->tx_currdescnum = 0;
+}
+
+static void rx_descs_init(struct dw_qos_eth_dev *priv)
+{
+ struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p;
+ struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
+ char *rxbuffs = &priv->rxbuffs[0];
+ struct dmamacdescr *desc_p;
+ u32 idx;
+
+ /* Before passing buffers to GMAC we need to make sure zeros
+ * written there right after "priv" structure allocation were
+ * flushed into RAM.
+ * Otherwise there's a chance to get some of them flushed in RAM when
+ * GMAC is already pushing data to RAM via DMA. This way incoming from
+ * GMAC data will be corrupted. */
+ flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
+
+ for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+ desc_p = &desc_table_p[idx];
+ desc_p->des0 = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->des1 = 0;
+ desc_p->des2 = 0;
+ desc_p->des3 = DESC_RXSTS_OWNBYDMA | DESC_RXSTS_BUF1V;
+ }
+
+ /* Flush all Rx buffer descriptors at once */
+ flush_dcache_range((ulong)priv->rx_mac_descrtable,
+ (ulong)priv->rx_mac_descrtable +
+ sizeof(priv->rx_mac_descrtable));
+
+ writel(0, &ch0_p->rxdescaddrhi);
+ writel((ulong)&desc_table_p[0], &ch0_p->rxdescaddrlo);
+ writel(CONFIG_RX_DESCR_NUM - 1, &ch0_p->rxdescringlen);
+ writel((ulong)&desc_table_p[CONFIG_RX_DESCR_NUM], &ch0_p->rxdesctail);
+ priv->rx_currdescnum = 0;
+}
+
+static int _dw_qos_write_hwaddr(struct dw_qos_eth_dev *priv, u8 *mac_id)
+{
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ u32 macid_lo, macid_hi;
+
+ macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
+ (mac_id[3] << 24);
+ macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+ writel(macid_hi, &mac_p->macaddr0hi);
+ writel(macid_lo, &mac_p->macaddr0lo);
+
+ return 0;
+}
+
+static void _dw_qos_eth_halt(struct dw_qos_eth_dev *priv)
+{
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p;
+
+ writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
+ writel(readl(&ch0_p->txcontrol) & ~(TXST), &ch0_p->txcontrol);
+ writel(readl(&ch0_p->rxcontrol) & ~(RXST), &ch0_p->rxcontrol);
+
+#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK
+ phy_shutdown(priv->phydev);
+#endif
+}
+
+static int _dw_qos_eth_init(struct dw_qos_eth_dev *priv, u8 *enetaddr)
+{
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
+ struct eth_dma_regs *dma_p = priv->dma_regs_p;
+ struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p;
+ struct eth_mtl_q0_regs *mtl_p = priv->mtl_q0_regs_p;
+ unsigned int start, burst;
+ int ret = 0;
+
+ writel(readl(&dma_p->dmamode) | DMAMAC_SRST, &dma_p->dmamode);
+
+ start = get_timer(0);
+ while (readl(&dma_p->dmamode) & DMAMAC_SRST) {
+ if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
+ printf("DMA reset timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ mdelay(100);
+ };
+
+ /*
+ * Soft reset above clears HW address registers.
+ * So we have to set it here once again.
+ */
+ _dw_qos_write_hwaddr(priv, enetaddr);
+
+ rx_descs_init(priv);
+ tx_descs_init(priv);
+
+ writel(PBLX8, &ch0_p->control);
+ /* enable TX queue store-and-forward mode */
+ writel(TXQ0_TSF, &mtl_p->txopmode);
+
+#ifdef CONFIG_DW_AXI_BURST_LEN
+ burst = CONFIG_DW_AXI_BURST_LEN / 8;
+#else
+ burst = 2;
+#endif
+ writel(TXST | (burst << TXPBLSHIFT), &ch0_p->txcontrol);
+ writel(RXST | (burst << RXPBLSHIFT) |
+ (CONFIG_ETH_BUFSIZE << RBSZSHIFT), &ch0_p->rxcontrol);
+
+#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK
+ /* Start up the PHY */
+ ret = phy_startup(priv->phydev);
+ if (ret) {
+ printf("Could not initialize PHY %s\n",
+ priv->phydev->dev->name);
+ return ret;
+ }
+
+ dw_qos_adjust_link(mac_p, priv->phydev);
+
+ if (!priv->phydev->link)
+ return -EIO;
+#else
+ /* just go into 1G full duplex mode and stay there */
+ writel(MII_PORTSELECT | FRAMEBURSTENABLE | DISABLERXOWN | FULLDPLXMODE,
+ &mac_p->conf);
+#endif
+
+ writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
+
+ return ret;
+}
+
+static int _dw_qos_eth_send(struct dw_qos_eth_dev *priv, void *packet,
+ int length)
+{
+ struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p;
+ u32 desc_num = priv->tx_currdescnum;
+ struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ ulong data_start = (ulong)&priv->txbuffs[desc_num * CONFIG_ETH_BUFSIZE];
+ ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+
+ /*
+ * Strictly we only need to invalidate the "txrx_status" field
+ * for the following check, but on some platforms we cannot
+ * invalidate only 4 bytes, so we flush the entire descriptor,
+ * which is 16 bytes in total. This is safe because the
+ * individual descriptors in the array are each aligned to
+ * ARCH_DMA_MINALIGN and padded appropriately.
+ */
+ invalidate_dcache_range(desc_start, desc_end);
+
+ /* Check if the descriptor is owned by CPU */
+ if (desc_p->des3 & DESC_TXSTS_OWNBYDMA) {
+ printf("CPU not owner of tx frame\n");
+ return -EPERM;
+ }
+
+ memcpy((void *)data_start, packet, length);
+
+ /* Flush data to be sent */
+ flush_dcache_range(data_start, data_end);
+
+ desc_p->des0 = data_start;
+ desc_p->des1 = 0;
+ desc_p->des2 = length & DESC_TXSTS_LENMASK;
+ desc_p->des3 = (length & DESC_TXSTS_LENMASK) | DESC_TXSTS_TXFIRST |
+ DESC_TXSTS_TXLAST;
+
+ desc_p->des3 |= DESC_TXSTS_OWNBYDMA;
+
+ /* Flush modified buffer descriptor */
+ flush_dcache_range(desc_start, desc_end);
+
+ /* Test the wrap-around condition. */
+ if (++desc_num >= CONFIG_TX_DESCR_NUM)
+ desc_num = 0;
+
+ priv->tx_currdescnum = desc_num;
+
+ /* Start the transmission */
+ writel((ulong)&priv->tx_mac_descrtable[CONFIG_TX_DESCR_NUM],
+ &ch0_p->txdesctail);
+
+ return 0;
+}
+
+static int _dw_qos_eth_recv(struct dw_qos_eth_dev *priv, uchar **packetp)
+{
+ u32 status, desc_num = priv->rx_currdescnum;
+ struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
+ int length = -EAGAIN;
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+ ulong data_start = (ulong)&priv->rxbuffs[desc_num * CONFIG_ETH_BUFSIZE];
+ ulong data_end;
+
+ /* Invalidate entire buffer descriptor */
+ invalidate_dcache_range(desc_start, desc_end);
+
+ status = desc_p->des3;
+
+ /* Check if the owner is the CPU */
+ if (!(status & DESC_RXSTS_OWNBYDMA)) {
+ length = (status & DESC_RXSTS_FRMLENMSK);
+
+ /* Invalidate received data */
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
+ *packetp = (uchar *)data_start;
+ }
+
+ return length;
+}
+
+static int _dw_qos_free_pkt(struct dw_qos_eth_dev *priv)
+{
+ u32 desc_num = priv->rx_currdescnum;
+ struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
+ ulong desc_start = (ulong)desc_p;
+ ulong desc_end = desc_start +
+ roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
+
+ desc_p->des0 = (ulong)&priv->rxbuffs[desc_num * CONFIG_ETH_BUFSIZE];
+ desc_p->des1 = 0;
+ desc_p->des2 = 0;
+ /*
+ * Make the current descriptor valid again and go to
+ * the next one
+ */
+ desc_p->des3 = DESC_RXSTS_OWNBYDMA | DESC_RXSTS_BUF1V;
+
+ /* Flush only status field - others weren't changed */
+ flush_dcache_range(desc_start, desc_end);
+
+ /* Test the wrap-around condition. */
+ if (++desc_num >= CONFIG_RX_DESCR_NUM)
+ desc_num = 0;
+ priv->rx_currdescnum = desc_num;
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+static int dw_qos_eth_init(struct eth_device *dev, bd_t *bis)
+{
+ return _dw_qos_eth_init(dev->priv, dev->enetaddr);
+}
+
+static int dw_qos_eth_send(struct eth_device *dev, void *packet, int length)
+{
+ return _dw_qos_eth_send(dev->priv, packet, length);
+}
+
+static int dw_qos_eth_recv(struct eth_device *dev)
+{
+ uchar *packet;
+ int length;
+
+ length = _dw_qos_eth_recv(dev->priv, &packet);
+ if (length == -EAGAIN)
+ return 0;
+ net_process_received_packet(packet, length);
+
+ _dw_qos_free_pkt(dev->priv);
+
+ return 0;
+}
+
+static void dw_qos_eth_halt(struct eth_device *dev)
+{
+ return _dw_qos_eth_halt(dev->priv);
+}
+
+static int dw_qos_write_hwaddr(struct eth_device *dev)
+{
+ return _dw_qos_write_hwaddr(dev->priv, dev->enetaddr);
+}
+
+int dw_qos_initialize(ulong base_addr, u32 interface)
+{
+ struct eth_device *dev;
+ struct dw_qos_eth_dev *priv;
+
+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ if (!dev)
+ return -ENOMEM;
+
+ /*
+ * Since the priv structure contains the descriptors which need a strict
+ * buswidth alignment, memalign is used to allocate memory
+ */
+ priv = (struct dw_qos_eth_dev *)memalign(ARCH_DMA_MINALIGN,
+ sizeof(struct dw_qos_eth_dev));
+ if (!priv) {
+ free(dev);
+ return -ENOMEM;
+ }
+
+ if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
+ printf("dw_qos: buffers are outside DMA memory\n");
+ return -EINVAL;
+ }
+
+ memset(dev, 0, sizeof(struct eth_device));
+ memset(priv, 0, sizeof(struct dw_qos_eth_dev));
+
+ sprintf(dev->name, "dwmac.%lx", base_addr);
+ dev->iobase = (int)base_addr;
+ dev->priv = priv;
+
+ priv->dev = dev;
+ priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
+ priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
+ DW_DMA_BASE_OFFSET);
+
+ dev->init = dw_qos_eth_init;
+ dev->send = dw_qos_eth_send;
+ dev->recv = dw_qos_eth_recv;
+ dev->halt = dw_qos_eth_halt;
+ dev->write_hwaddr = dw_qos_write_hwaddr;
+
+ eth_register(dev);
+
+ priv->interface = interface;
+
+#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK
+ dw_qos_mdio_init(dev->name, priv->mac_regs_p);
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+
+ return dw_qos_phy_init(priv, dev);
+#else
+ return 0;
+#endif
+}
+#endif
+
+#ifdef CONFIG_DM_ETH
+static int dw_qos_eth_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return _dw_qos_eth_init(dev->priv, pdata->enetaddr);
+}
+
+static int dw_qos_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+
+ return _dw_qos_eth_send(priv, packet, length);
+}
+
+static int dw_qos_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+
+ return _dw_qos_eth_recv(priv, packetp);
+}
+
+static int dw_qos_eth_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+
+ return _dw_qos_free_pkt(priv);
+}
+
+static void dw_qos_eth_stop(struct udevice *dev)
+{
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+
+ return _dw_qos_eth_halt(priv);
+}
+
+static int dw_qos_eth_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+
+ return _dw_qos_write_hwaddr(priv, pdata->enetaddr);
+}
+
+static int dw_qos_eth_bind(struct udevice *dev)
+{
+#ifdef CONFIG_DM_PCI
+ static int num_cards;
+ char name[20];
+
+ /* Create a unique device name for PCI type devices */
+ if (device_is_on_pci_bus(dev)) {
+ sprintf(name, "eth_dw_qos#%u", num_cards++);
+ device_set_name(dev, name);
+ }
+#endif
+
+ return 0;
+}
+
+static int dw_qos_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+ u32 iobase = pdata->iobase;
+ ulong ioaddr;
+ int ret;
+
+#ifdef CONFIG_DM_PCI
+ /*
+ * If we are on PCI bus, either directly attached to a PCI root port,
+ * or via a PCI bridge, fill in platdata before we probe the hardware.
+ */
+ if (device_is_on_pci_bus(dev)) {
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
+ iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+ iobase = dm_pci_mem_to_phys(dev, iobase);
+
+ pdata->iobase = iobase;
+ pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
+ }
+#endif
+
+ debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
+ ioaddr = iobase;
+ priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
+ priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
+ priv->dma_ch0_regs_p =
+ (struct eth_dma_ch0_regs *)(ioaddr + DW_DMA_CH0_BASE_OFFSET);
+ priv->mtl_q0_regs_p =
+ (struct eth_mtl_q0_regs *)(ioaddr + DW_MTL_Q0_BASE_OFFSET);
+ priv->interface = pdata->phy_interface;
+ priv->max_speed = pdata->max_speed;
+
+#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK
+ dw_qos_mdio_init(dev->name, dev);
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+
+ ret = dw_qos_phy_init(priv, dev);
+#else
+ ret = 0;
+#endif
+ debug("%s, ret=%d\n", __func__, ret);
+
+ return ret;
+}
+
+static int dw_qos_eth_remove(struct udevice *dev)
+{
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+
+ free(priv->phydev);
+#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+#endif
+
+ return 0;
+}
+
+static const struct eth_ops dw_qos_eth_ops = {
+ .start = dw_qos_eth_start,
+ .send = dw_qos_eth_send,
+ .recv = dw_qos_eth_recv,
+ .free_pkt = dw_qos_eth_free_pkt,
+ .stop = dw_qos_eth_stop,
+ .write_hwaddr = dw_qos_eth_write_hwaddr,
+};
+
+static int dw_qos_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dw_qos_eth_pdata *dw_qos_pdata = dev_get_platdata(dev);
+#ifdef CONFIG_DM_GPIO
+ struct dw_qos_eth_dev *priv = dev_get_priv(dev);
+#endif
+ struct eth_pdata *pdata = &dw_qos_pdata->eth_pdata;
+ const char *phy_mode;
+ const fdt32_t *cell;
+#ifdef CONFIG_DM_GPIO
+ int reset_flags = GPIOD_IS_OUT;
+#endif
+ int ret = 0;
+
+ pdata->iobase = (ulong)dev_map_physmem(dev, 0x2000);
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ pdata->max_speed = 0;
+ cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
+ if (cell)
+ pdata->max_speed = fdt32_to_cpu(*cell);
+
+#ifdef CONFIG_DM_GPIO
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &priv->reset_gpio, reset_flags);
+ if (ret == 0) {
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "snps,reset-delays-us", dw_qos_pdata->reset_delays, 3);
+ } else if (ret == -ENOENT) {
+ ret = 0;
+ }
+#endif
+
+ return ret;
+}
+
+static const struct udevice_id dw_qos_eth_ids[] = {
+ { .compatible = "snps,dwc-qos-ethernet-4.10" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_dw_qos) = {
+ .name = "eth_dw_qos",
+ .id = UCLASS_ETH,
+ .of_match = dw_qos_eth_ids,
+ .ofdata_to_platdata = dw_qos_eth_ofdata_to_platdata,
+ .bind = dw_qos_eth_bind,
+ .probe = dw_qos_eth_probe,
+ .remove = dw_qos_eth_remove,
+ .ops = &dw_qos_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct dw_qos_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct dw_qos_eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static struct pci_device_id supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
+ { }
+};
+
+U_BOOT_PCI_DEVICE(eth_dw_qos, supported);
+#endif
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
new file mode 100644
index 0000000..cfe12e1
--- /dev/null
+++ b/drivers/net/dwc_eth_qos.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2016
+ * National Instruments
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DW_ETH_QOS_H
+#define _DW_ETH_QOS_H
+
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
+
+#define CONFIG_TX_DESCR_NUM 16
+#define CONFIG_RX_DESCR_NUM 16
+#define CONFIG_ETH_BUFSIZE 2048
+#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
+
+struct eth_mac_regs {
+ u32 conf; /* 0x00 */
+ u32 ext_conf; /* 0x04 */
+ u32 reserved_1[42];
+ u32 intstatus; /* 0xb0 */
+ u32 intenable; /* 0xb4 */
+ u32 rx_tx_status; /* 0xb8 */
+ u32 reserved_2[81];
+ u32 miiaddr; /* 0x200 */
+ u32 miidata; /* 0x204 */
+ u32 reserved_3[62];
+ u32 macaddr0hi; /* 0x300 */
+ u32 macaddr0lo; /* 0x304 */
+};
+
+/* MAC configuration register definitions */
+#define FRAMEBURSTENABLE (1 << 18)
+#define MII_PORTSELECT (1 << 15)
+#define FES_100 (1 << 14)
+#define DISABLERXOWN (1 << 10)
+#define FULLDPLXMODE (1 << 13)
+#define RXENABLE (1 << 0)
+#define TXENABLE (1 << 1)
+
+/* MII address register definitions */
+#define MII_BUSY (1 << 0)
+#define MII_WRITE (1 << 2)
+#define MII_READ (3 << 2)
+#define MII_CLKRANGE_60_100M (0)
+#define MII_CLKRANGE_100_150M (0x1)
+#define MII_CLKRANGE_20_35M (0x2)
+#define MII_CLKRANGE_35_60M (0x3)
+#define MII_CLKRANGE_150_250M (0x4)
+#define MII_CLKRANGE_250_300M (0x5)
+
+#define MIIADDRSHIFT (21)
+#define MIIREGSHIFT (16)
+#define MIICLKSHIFT (8)
+#define MII_REGMSK (0x1F << 16)
+#define MII_ADDRMSK (0x1F << 21)
+#define MII_CLKMSK (0xF << 8);
+
+struct eth_mtl_q0_regs {
+ u32 txopmode; /* 0x00 */
+ u32 reserved_1[5];
+ u32 rxopmode; /* 0x30 */
+};
+
+#define DW_MTL_Q0_BASE_OFFSET (0xd00)
+
+/* TX queue 0 operation mode definitions */
+#define TXQ0_TSF (1 << 1)
+
+struct eth_dma_regs {
+ u32 dmamode; /* 0x00 */
+ u32 sysbusmode; /* 0x04 */
+ u32 status; /* 0x08 */
+ u32 debug0; /* 0x0c */
+ u32 debug1; /* 0x10 */
+ u32 debug2; /* 0x14 */
+ u32 reserved_1[3];
+ u32 axi_ace_ar; /* 0x20 */
+ u32 axi_ace_aw; /* 0x24 */
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
+ u32 currhosttxdesc; /* 0x48 */
+ u32 currhostrxdesc; /* 0x4c */
+ u32 currhosttxbuffaddr; /* 0x50 */
+ u32 currhostrxbuffaddr; /* 0x54 */
+};
+
+#define DW_DMA_BASE_OFFSET (0x1000)
+
+/* Default DMA Burst length */
+#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
+#endif
+
+/* DMA mode register definitions */
+#define PRIORXTX_41 (3 << 12)
+#define PRIORXTX_31 (2 << 12)
+#define PRIORXTX_21 (1 << 12)
+#define PRIORXTX_11 (0 << 12)
+#define TXHIGHPRIO (1 << 11)
+#define DMAMAC_SRST (1 << 0)
+
+struct eth_dma_ch0_regs {
+ u32 control; /* 0x00 */
+ u32 txcontrol; /* 0x04 */
+ u32 rxcontrol; /* 0x08 */
+ u32 reserved_1; /* 0x0c */
+ u32 txdescaddrhi; /* 0x10 */
+ u32 txdescaddrlo; /* 0x14 */
+ u32 rxdescaddrhi; /* 0x18 */
+ u32 rxdescaddrlo; /* 0x1c */
+ u32 txdesctail; /* 0x20 */
+ u32 reserved_2; /* 0x24 */
+ u32 rxdesctail; /* 0x28 */
+ u32 txdescringlen; /* 0x2c */
+ u32 rxdescringlen; /* 0x30 */
+ u32 reserved_3[12];
+ u32 status; /* 0x60 */
+};
+
+#define DW_DMA_CH0_BASE_OFFSET (0x1100)
+
+/* DMA control definitions */
+#define PBLX8 (1 << 16)
+
+/* DMA TX control definitions */
+#define TXST (1 << 0)
+
+#define TXPBLSHIFT (16)
+#define TXPBLMASK (0x3F << 16)
+
+/* DMA RX control definitions */
+#define RXST (1 << 0)
+
+#define RXPBLSHIFT (16)
+#define RBSZSHIFT (1)
+#define RXPBLMASK (0x3F << 16)
+#define RBSZMASK (0x7FFF << 1)
+
+/* Descriptior related definitions */
+#define MAC_MAX_FRAME_SZ (1600)
+
+struct dmamacdescr {
+ u32 des0;
+ u32 des1;
+ u32 des2;
+ u32 des3;
+} __packed;
+
+/*
+ * txrx_status definitions
+ */
+
+/* tx status bits definitions */
+/* des2 */
+#define DESC_TXSTS_TXINT (1 << 31)
+
+/* des3 */
+#define DESC_TXSTS_OWNBYDMA (1 << 31)
+#define DESC_TXSTS_CTXT (1 << 30)
+#define DESC_TXSTS_TXFIRST (1 << 29)
+#define DESC_TXSTS_TXLAST (1 << 28)
+#define DESC_TXSTS_LENMASK (0x1FFF << 0)
+
+/* rx status bits definitions */
+/* des3 */
+#define DESC_RXSTS_OWNBYDMA (1 << 31)
+#define DESC_RXSTS_CTXT (1 << 30)
+#define DESC_RXSTS_RXFIRST (1 << 29)
+#define DESC_RXSTS_RXLAST (1 << 28)
+#define DESC_RXSTS_BUF1V (1 << 24)
+#define DESC_RXSTS_ERROR (1 << 15)
+#define DESC_RXSTS_FRMLENMSK (0x7FFF << 0)
+
+/*
+ * dmamac_cntl definitions
+ */
+
+struct dw_qos_eth_dev {
+ struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+ struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+ char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+ char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+
+ u32 interface;
+ u32 max_speed;
+ u32 tx_currdescnum;
+ u32 rx_currdescnum;
+
+ struct eth_mac_regs *mac_regs_p;
+ struct eth_dma_regs *dma_regs_p;
+ struct eth_dma_ch0_regs *dma_ch0_regs_p;
+ struct eth_mtl_q0_regs *mtl_q0_regs_p;
+#ifndef CONFIG_DM_ETH
+ struct eth_device *dev;
+#endif
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc reset_gpio;
+#endif
+
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+};
+
+#ifdef CONFIG_DM_ETH
+struct dw_qos_eth_pdata {
+ struct eth_pdata eth_pdata;
+ u32 reset_delays[3];
+};
+#endif
+
+#endif
--
2.1.4
More information about the U-Boot
mailing list