[U-Boot] [PATCH V2 4/4] ARM: tegra186: call secure monitor for all cache-wide ops

[Stephen Warren]

From: Stephen Warren <swarren at nvidia.com>

An SMC call is required for all cache-wide operations on Tegra186. This
patch implements the two missing hooks now that U-Boot supports them, and
fixes the mapping of "hook name" to SMC call code.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: Implement the functions in assembly.
---
 arch/arm/mach-tegra/tegra186/cache.S | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra186/cache.S b/arch/arm/mach-tegra/tegra186/cache.S
index 3ca3f3c8af68..3061dc2ecff2 100644
--- a/arch/arm/mach-tegra/tegra186/cache.S
+++ b/arch/arm/mach-tegra/tegra186/cache.S
@@ -9,10 +9,10 @@
 
 #define SMC_SIP_INVOKE_MCE		0x82FFFF00
 #define MCE_SMC_ROC_FLUSH_CACHE		(SMC_SIP_INVOKE_MCE | 11)
+#define MCE_SMC_ROC_FLUSH_CACHE_ONLY	(SMC_SIP_INVOKE_MCE | 14)
+#define MCE_SMC_ROC_CLEAN_CACHE_ONLY	(SMC_SIP_INVOKE_MCE | 15)
 
-ENTRY(__asm_flush_l3_dcache)
-	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
-	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
+ENTRY(__asm_tegra_cache_smc)
 	mov	x1, #0
 	mov	x2, #0
 	mov	x3, #0
@@ -22,4 +22,22 @@ ENTRY(__asm_flush_l3_dcache)
 	smc	#0
 	mov	x0, #0
 	ret
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_invalidate_l3_dcache)
+	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
+	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
+	b	__asm_tegra_cache_smc
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_flush_l3_dcache)
+	mov	x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
+	movk	x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
+	b	__asm_tegra_cache_smc
 ENDPROC(__asm_flush_l3_dcache)
+
+ENTRY(__asm_invalidate_l3_icache)
+	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
+	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
+	b	__asm_tegra_cache_smc
+ENDPROC(__asm_invalidate_l3_icache)
-- 
2.10.1