[U-Boot] [RFC PATCH v1 5/6] mtd: nand: pxa3xx-nand: fix random command timeouts

[Chris Packham]

When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase

Cc: Robert Jarzmik <robert.jarzmik at free.fr>
Signed-off-by: Chris Packham <judge.packham at gmail.com>
---

 drivers/mtd/nand/pxa3xx_nand.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 3c065169ce9c..9a43bd11a453 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -619,8 +619,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
 		is_ready = 1;
 	}
 
+	/*
+	 * Clear all status bit before issuing the next command, which
+	 * can and will alter the status bits and will deserve a new
+	 * interrupt on its own. This lets the controller exit the IRQ
+	 */
+	nand_writel(info, NDSR, status);
+
 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(info, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
 		info->state = STATE_CMD_HANDLE;
 
@@ -641,8 +647,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}
 
-	/* clear NDSR to let the controller exit the IRQ */
-	nand_writel(info, NDSR, status);
 	if (is_completed)
 		info->cmd_complete = 1;
 	if (is_ready)
-- 
2.10.0.479.g7c56b16