[U-Boot] [PATCH] Kconfig: ifc: Moving IFC_BANK_COUNT from Kconfig to config.h
Prabhakar Kushwaha
prabhakar.kushwaha at nxp.com
Fri Oct 21 06:37:18 CEST 2016
Migration of IFC_BANK_COUNT from Kconfig to config.h avoids adding
SoC name in Kconfig as Dependencies. It will help in having
all SoC related defines in config.h - easy to maintain.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
---
This patch provide base for defining SYS_FSL_IFC_CLK_DIV required
for v3 version of below patch-set
http://patchwork.ozlabs.org/patch/666844/
http://patchwork.ozlabs.org/patch/666849/
http://patchwork.ozlabs.org/patch/666848/
README | 3 +++
arch/arm/cpu/armv7/ls102xa/Kconfig | 5 -----
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 -------
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/powerpc/include/asm/config_mpc85xx.h | 18 +++++++++---------
drivers/misc/fsl_ifc.c | 2 +-
drivers/mtd/nand/fsl_ifc_nand.c | 6 +++---
include/fsl_ifc.h | 20 ++++++++++----------
9 files changed, 31 insertions(+), 35 deletions(-)
diff --git a/README b/README
index 68d6a49..c83171a 100644
--- a/README
+++ b/README
@@ -507,6 +507,9 @@ The following options need to be configured:
Board config to use DDR4. It can be enabled for SoCs with
DDR4 controllers.
+ SYS_FSL_IFC_BANK_COUNT
+ Maximum banks of Integrated flash controller
+
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 28bf778..68d03ab 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -81,9 +81,4 @@ config SYS_FSL_DDR4
help
Enable Freescale DDR4 controller.
-config SYS_FSL_IFC_BANK_COUNT
- int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1021A
- default 8
-
endmenu
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..0587559 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -71,13 +71,6 @@ config NUM_DDR_CONTROLLERS
default 3 if ARCH_LS2080A
default 1
-config SYS_FSL_IFC_BANK_COUNT
- int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
- default 4 if ARCH_LS1043A
- default 4 if ARCH_LS1046A
- default 8 if ARCH_LS2080A
-
config SYS_FSL_HAS_DP_DDR
bool
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 4201e0f..28d3974 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -27,6 +27,8 @@
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
+#define SYS_FSL_IFC_BANK_COUNT 8
+
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
@@ -150,6 +152,7 @@
/* SoC related */
#ifdef CONFIG_LS1043A
+#define SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
@@ -187,6 +190,7 @@
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#elif defined(CONFIG_ARCH_LS1046A)
+#define SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ec65cc0..d65f5bf 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -120,6 +120,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#define SYS_FSL_IFC_BANK_COUNT 8
#else
#error SoC not defined
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e8..073a7b5 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -150,7 +150,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -590,7 +590,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
+#define SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -612,7 +612,7 @@
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
+#define SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -667,7 +667,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
@@ -714,7 +714,7 @@
#define CONFIG_SYS_ULB_CLK 4
#define CONFIG_SYS_ETVPE_CLK 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -786,7 +786,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FSL_ERRATUM_A008044
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
@@ -838,7 +838,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
per rcw field value */
@@ -895,7 +895,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
per rcw field value */
#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -924,7 +924,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index a33efdb..c3e59f0 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -13,7 +13,7 @@ void print_ifc_regs(void)
int i, j;
printf("IFC Controller Registers\n");
- for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
+ for (i = 0; i < SYS_FSL_IFC_BANK_COUNT; i++) {
printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
i, get_ifc_cspr(i), i, get_ifc_amask(i),
i, get_ifc_csor(i));
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index bc6bdc9..d3ad210 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -19,11 +19,11 @@
#include <linux/errno.h>
#include <fsl_ifc.h>
-#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#ifndef SYS_FSL_IFC_BANK_COUNT
+#define SYS_FSL_IFC_BANK_COUNT 4
#endif
-#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define MAX_BANKS SYS_FSL_IFC_BANK_COUNT
#define ERR_BYTE 0xFF /* Value returned for read bytes
when read failed */
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index a86f216..29c98a1 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -939,21 +939,21 @@ struct fsl_ifc_gpcm {
u32 gpcm_stat;
};
-#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
-#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#ifdef SYS_FSL_IFC_BANK_COUNT
+#if (SYS_FSL_IFC_BANK_COUNT <= 8)
#define IFC_CSPR_REG_LEN 148
#define IFC_AMASK_REG_LEN 144
#define IFC_CSOR_REG_LEN 144
#define IFC_FTIM_REG_LEN 576
#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
- CONFIG_SYS_FSL_IFC_BANK_COUNT
+ SYS_FSL_IFC_BANK_COUNT
#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
- CONFIG_SYS_FSL_IFC_BANK_COUNT
+ SYS_FSL_IFC_BANK_COUNT
#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
- CONFIG_SYS_FSL_IFC_BANK_COUNT
+ SYS_FSL_IFC_BANK_COUNT
#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
- CONFIG_SYS_FSL_IFC_BANK_COUNT
+ SYS_FSL_IFC_BANK_COUNT
#else
#error IFC BANK count not vaild
#endif
@@ -991,13 +991,13 @@ struct fsl_ifc_ftim {
struct fsl_ifc_fcm {
u32 ifc_rev;
u32 res1[0x2];
- struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ struct fsl_ifc_cspr cspr_cs[SYS_FSL_IFC_BANK_COUNT];
u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
- struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ struct fsl_ifc_amask amask_cs[SYS_FSL_IFC_BANK_COUNT];
u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
- struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ struct fsl_ifc_csor csor_cs[SYS_FSL_IFC_BANK_COUNT];
u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
- struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ struct fsl_ifc_ftim ftim_cs[SYS_FSL_IFC_BANK_COUNT];
u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
u32 rb_stat;
u32 rb_map;
--
2.7.4
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