[U-Boot] [PATCH v3 1/3] armv8/ls1043a: fixup GIC offset according to SVR and SCFG_GIC400_ALIGN[GIC_ADDR_BIT]

[york sun]

On 10/21/2016 03:28 AM, Wenbin song wrote:
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
> and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
> which offset will be used.
>
> If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used.
> 64K alignment is the default setting.
>
> Overriding the weekly smp_kick_all_cpus, the new impletment is able to detect
> GIC offset.
>
> Signed-off-by: Wenbin Song <wenbin.song at nxp.com>
> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> ---
> Changes in v3:
> 	Add description about smp_kick_all_cpus on commit message.
> 	Rename the macros on commit message to match with them used in the change.
> 	Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.     		
> Changes in v2:
> 	None
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig         |  4 ++
>  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S      | 47 +++++++++++++++++++++++
>  arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +++++-
>  3 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 94ec8d5..c66c497 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -12,6 +12,7 @@ config ARCH_LS1043A
>  	select SYS_FSL_DDR_VER_50
>  	select SYS_FSL_ERRATUM_A010315
>  	select SYS_FSL_ERRATUM_A010539
> +	select HAS_FEATURE_GIC4K_ALIGN
>
>  config ARCH_LS1046A
>  	bool
> @@ -135,4 +136,7 @@ config SYS_FSL_DDR4
>  	help
>  	  Enable Freescale DDR4 controller.
>
> +config HAS_FEATURE_GIC4K_ALIGN
> +       bool
> +
>  endmenu
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> index 5d0b7a4..f0da559 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> @@ -14,6 +14,40 @@
>  #include <asm/arch/mp.h>
>  #endif
>
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> +
> +/* fixup GIC offset */
> +ENTRY(fix_gic_offset)

Nitpick. It would be easier to understand if you have some comments to 
show the input and output of such function.

> +	ldr     x0, =GICD_BASE
> +	ldr     x1, =GICC_BASE
> +	ldr     x3, =DCFG_CCSR_SVR
> +	ldr	w3, [x3]
> +	rev	w3, w3
> +	ands	w3, w3, #0xff
> +	cmp	w3, #REV1_0
> +	b.eq	1f
> +	ldr	x3, =SCFG_GIC400_ALIGN
> +	ldr	w3, [x3]
> +	rev	w3, w3
> +	tbnz	w3, #GIC_ADDR_BIT, 1f
> +	ret
> +1:
> +	ldr     x0, =GICD_BASE_4K
> +	ldr     x1, =GICC_BASE_4K
> +	ret
> +ENDPROC(fix_gic_offset)
> +
> +ENTRY(smp_kick_all_cpus)
> +	/* Kick secondary cpus up by SGI 0 interrupt */
> +	mov	x29, lr			/* Save LR */
> +	bl	fix_gic_offset
> +	bl	gic_kick_secondary_cpus
> +	mov	lr, x29			/* Restore LR */
> +	ret
> +ENDPROC(smp_kick_all_cpus)
> +
> +#endif
> +
>  ENTRY(lowlevel_init)
>  	mov	x29, lr			/* Save LR */
>
> @@ -105,15 +139,23 @@ ENTRY(lowlevel_init)
>  	/* Initialize GIC Secure Bank Status */
>  #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
>  	branch_if_slave x0, 1f
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> +	bl	fix_gic_offset
> +#else
>  	ldr	x0, =GICD_BASE
> +#endif
>  	bl	gic_init_secure
>  1:
>  #ifdef CONFIG_GICV3
>  	ldr	x0, =GICR_BASE
>  	bl	gic_init_secure_percpu
>  #elif defined(CONFIG_GICV2)
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> +	bl	fix_gic_offset
> +#else
>  	ldr	x0, =GICD_BASE
>  	ldr	x1, =GICC_BASE
> +#endif
>  	bl	gic_init_secure_percpu
>  #endif
>  #endif
> @@ -335,7 +377,12 @@ ENTRY(secondary_boot_func)
>  #if defined(CONFIG_GICV3)
>  	gic_wait_for_interrupt_m x0
>  #elif defined(CONFIG_GICV2)
> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> +	bl	fix_gic_offset
> +	mov	x0, x1
> +#else
>          ldr     x0, =GICC_BASE
> +#endif
>          gic_wait_for_interrupt_m x0, w1
>  #endif
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index 4201e0f..eb6e58d 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -172,8 +172,16 @@
>  #define SMMU_BASE		0x09000000
>
>  /* Generic Interrupt Controller Definitions */
> -#define GICD_BASE		0x01401000
> -#define GICC_BASE		0x01402000
> +#define GICD_BASE		0x01410000
> +#define GICC_BASE		0x01420000
> +#define GICD_BASE_4K            0x01401000
> +#define GICC_BASE_4K            0x01402000
> +
> +#define DCFG_CCSR_SVR		0x1ee00a4
> +#define REV1_0			0x10
> +#define REV1_1			0x11
> +#define GIC_ADDR_BIT		31
> +#define SCFG_GIC400_ALIGN	0x1570188
>
>  #define CONFIG_SYS_FSL_ERRATUM_A008850
>  #define CONFIG_SYS_FSL_ERRATUM_A009663
>

Reviewed-by: York Sun <york.sun at nxp.com>