[U-Boot] [PATCH v3 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for LS1043A rev1.0

[Wenbin Song]

hi

Best Regards
Wenbin Song

> -----Original Message-----
> From: york sun
> Sent: Friday, October 21, 2016 10:16 PM
> To: Wenbin Song <wenbin.song at nxp.com>; albert.u.boot at aribaud.net;
> Mingkai Hu <mingkai.hu at nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 2/3] armv8/fsl-layerscape: fdt: fixup GIC node for
> LS1043A rev1.0
> 
> On 10/21/2016 03:28 AM, Wenbin song wrote:
> > The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> > alignment and 64K alignment. 4K alignment is consistent with rev1.0
> implement.
> >
> > The default GIC offset in kernel device tree is using 64K alignment,
> > if rev1.0 silicon used, need to fixup the GIC node to use 4K alignment.
> >
> > Signed-off-by: Wenbin Song <wenbin.song at nxp.com>
> > Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
> > ---
> > Changes for v3:
> > 	Replace CONFIG_LS1043A with HAS_FEATURE_GIC4K_ALIGN.
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/fdt.c            | 49
> ++++++++++++++++++++++
> >  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  3 +-
> >  2 files changed, 51 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > index 1a8321b..54f8492 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> > @@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob)
> >  	}
> >  }
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> > +/* Fixup gic node align with 4K */
> > +static void fdt_fixup_gic(void *blob) {
> > +	int offset, err;
> > +	u64 reg[8];
> > +	struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > +	unsigned int val;
> > +	struct ccsr_scfg __iomem *scfg = (void
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> > +
> > +	val = gur_in32(&gur->svr) & 0xff;
> > +
> > +	if (val == REV1_1) {
> > +		val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
> > +		if (!val)
> > +			return;
> > +	}
> 
> For rev 1.0 SoC, it runs through here, right? If that what you want?
[wenbin]  For rev1.0 , it should be fixed, too. Because  rev1.0 is  using 4K offset alignment, but the default is using 64K alignment.
	     I will give some descriptions on commit message about it. 


> > +
> > +	offset = fdt_subnode_offset(blob, 0, "interrupt-controller at 1400000");
> > +	if (offset < 0) {
> > +		printf("WARNING: fdt_subnode_offset can't find
> node %s: %s\n",
> > +		       "interrupt-controller at 1400000", fdt_strerror(offset));
> > +		return;
> > +	}
> > +
> > +	reg[0] = cpu_to_fdt64(0x1401000);
> > +	reg[1] = cpu_to_fdt64(0x1000);
> > +	reg[2] = cpu_to_fdt64(0x1402000);
> > +	reg[3] = cpu_to_fdt64(0x2000);
> > +	reg[4] = cpu_to_fdt64(0x1404000);
> > +	reg[5] = cpu_to_fdt64(0x2000);
> > +	reg[6] = cpu_to_fdt64(0x1406000);
> > +	reg[7] = cpu_to_fdt64(0x2000);
> 
> What are these magic numbers?
[wenbin]  they are the offset and size for each GIC components.  I will redefine them using macros.     
> 
> > +
> > +	err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
> > +	if (err < 0) {
> > +		printf("WARNING: fdt_setprop can't set %s from
> node %s: %s\n",
> > +		       "reg", "interrupt-controller at 1400000",
> > +		       fdt_strerror(err));
> > +		return;
> > +	}
> > +
> > +	return;
> > +}
> > +#endif
> > +
> >  void ft_cpu_setup(void *blob, bd_t *bd)  {  #ifdef CONFIG_FSL_LSCH2
> > @@ -170,4 +216,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)  #endif
> >  	fsl_fdt_disable_usb(blob);
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN
> > +	fdt_fixup_gic(blob);
> > +#endif
> >  }
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > index d88543d..1dfef53 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> > @@ -359,7 +359,8 @@ struct ccsr_scfg {
> >  	u32 qspi_cfg;
> >  	u8 res_160[0x180-0x160];
> >  	u32 dmamcr;
> > -	u8 res_184[0x18c-0x184];
> > +	u8 res_184[0x188-0x184];
> > +	u32 gic_align;
> >  	u32 debug_icid;
> >  	u8 res_190[0x1a4-0x190];
> >  	u32 snpcnfgcr;
> >
> 
> Would it be reasonable to squash this patch with previous one in this set? They
> both deal with the same thing. If you run git bisect between this two, you don't
> get correct gic offset in device tree, do you?
> 
[wenbin]yes , I will squash it . 
> York