[U-Boot] [PATCH 5/5][v2] armv8/fsl-lsch3: Update code to release secondary cores

[york sun]

On 10/24/2016 08:49 AM, york.sun at nxp.com wrote:
> On 10/24/2016 01:33 AM, Priyanka Jain wrote:
>> NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
>> But other new SoCs like LS2088A, LS1088A release secondary
>> cores one by one to avoid power spike.
>>
>> Update code to release secondary cores based on SoC SVR
>> Add code to release cores one by one for non LS2080A SoCs
>>
>> Signed-off-by: Priyanka Jain <priyanka.jain at nxp.com>
>> Signed-off-by: Raghav Dogra <raghav.dogra at nxp.com>
>> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
>> ---
>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    2 +-
>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.h |    1 +
>>  arch/arm/cpu/armv8/fsl-layerscape/mp.c  |   59
>> ++++++++++++++++++++++++++++--
>>  3 files changed, 57 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> index ce04e48..15d157c 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> @@ -190,7 +190,7 @@ void enable_caches(void)
>>  }
>>  #endif
>>
>> -static inline u32 initiator_type(u32 cluster, int init_id)
>> +inline u32 initiator_type(u32 cluster, int init_id)
>>  {
>>      struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>>      u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> index 8072f3c..a05f8aa 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
>> @@ -5,4 +5,5 @@
>>   */
>>
>>  int fsl_qoriq_core_to_cluster(unsigned int core);
>> +u32 initiator_type(u32 cluster, int init_id);
>>  u32 cpu_mask(void);
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> index f607c39..5cf080f 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
>> @@ -9,6 +9,8 @@
>>  #include <asm/system.h>
>>  #include <asm/arch/mp.h>
>>  #include <asm/arch/soc.h>
>> +#include "cpu.h"
>> +#include <asm/arch-fsl-layerscape/soc.h>
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -22,11 +24,30 @@ phys_addr_t determine_mp_bootpg(void)
>>      return (phys_addr_t)&secondary_boot_code;
>>  }
>>
>> +#ifdef CONFIG_FSL_LSCH3
>> +void wake_secondary_core_n(int cluster, int core, int cluster_cores)
>> +{
>> +    struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>> +    struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
>> +    u32 mpidr = 0;
>> +
>> +    mpidr = ((cluster << 8) | core);
>> +    gur_out32(&gur->scratchrw[6], mpidr);
>
> What's the definition of each bit for scratchrw[6]? Before this patch,
> secondary cores only check if it is zero.
>
>> +    asm volatile("dsb st" : : : "memory");
>> +    rst->brrl |= 1 << ((cluster * cluster_cores) + core);
>> +    asm volatile("dsb st" : : : "memory");
>> +    while (gur_in32(&gur->scratchrw[6]) != 0)
>> +        ;
>
> Does each secondary core clear this register after it starts to run?
>

Priyanka,

I got hold of the architect for the bootrom. I understand the story 
behind the release one-by-one now. It would be better if you can add 
some comments for scratchrw[6] for its expected behaviour.

York