[U-Boot] [PATCH v1 1/4] sf: add ADDR_4B for 4byte address support

[Yao Yuan]

On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao <yao.yuan at freescale.com> wrote:
> > From: Yuan Yao <yao.yuan at nxp.com>
> >
> > Some new flash don't support bar register but use 4bytes address to
> > support exceed 16MB flash size.
> > So add flash flag:
> > ADDR_4B
> > for some flash which support 4bytes address.
> >
> > Signed-off-by: Yuan Yao <yao.yuan at nxp.com>
> > ---
> >  drivers/mtd/spi/sf_internal.h |  4 +++-
> >  drivers/mtd/spi/sf_params.c   |  2 +-
> >  drivers/mtd/spi/spi_flash.c   | 38 +++++++++++++++++++++++++-------------
> >  include/spi_flash.h           |  1 +
> >  4 files changed, 30 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/sf_internal.h
> > b/drivers/mtd/spi/sf_internal.h index cde4cfb..9ae1549 100644
> > --- a/drivers/mtd/spi/sf_internal.h
> > +++ b/drivers/mtd/spi/sf_internal.h
> > @@ -26,7 +26,8 @@ enum spi_nor_option_flags {  };
> >
> >  #define SPI_FLASH_3B_ADDR_LEN          3
> > -#define SPI_FLASH_CMD_LEN              (1 + SPI_FLASH_3B_ADDR_LEN)
> > +#define SPI_FLASH_4B_ADDR_LEN          4
> > +#define SPI_FLASH_CMD_MAX_LEN          (1 + SPI_FLASH_4B_ADDR_LEN)
> >  #define SPI_FLASH_16MB_BOUN            0x1000000
> >
> >  /* CFI Manufacture ID's */
> > @@ -130,6 +131,7 @@ struct spi_flash_params {
> >  #define RD_DUAL                        BIT(5)
> >  #define RD_QUADIO              BIT(6)
> >  #define RD_DUALIO              BIT(7)
> > +#define ADDR_4B                        BIT(8)
> >  #define RD_FULL                        (RD_QUAD | RD_DUAL | RD_QUADIO |
> RD_DUALIO)
> >  };
> >
> > diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
> > index 5b50114..9c26cc8 100644
> > --- a/drivers/mtd/spi/sf_params.c
> > +++ b/drivers/mtd/spi/sf_params.c
> > @@ -68,7 +68,7 @@ const struct spi_flash_params spi_flash_params_table[]
> = {
> >         {"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL |
> WR_QPP},
> >         {"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL |
> WR_QPP},
> >         {"S25FL256S_64K",  0x010219, 0x4d01,    64 * 1024,   512, RD_FULL |
> WR_QPP},
> > -       {"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL |
> WR_QPP},
> > +       {"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL |
> WR_QPP | ADDR_4B},
> 
> Sorry for the late, It's better to not relay on specific flash and do the 4-byte
> addressing. So, I've sent some patches based on this [1] and will send the next
> version to wind-up all these changes. Please wait some time.
> 

Ok, hope for it. We need change a lot and prepare for embrace more.
BTW, I'm working on a QSPI NAND flash support, a lot of the differences with NOR flash.

Do you think is it better to have a drivers/mtd/spi/spi_nand_flash.c ?