[U-Boot] [PATCH v2] powerpc/t2080: CPU erratum A-007907

[york sun]

On 10/24/2016 02:16 PM, york.sun at nxp.com wrote:
>> +
>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
>> +    flush_dcache();
>> +    mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
>> +    sync();
>> +#endif
>> +
>
> My erratum document shows a second step is to insert sync instruction
> before each dcbtls CT=0 or dcbtstls CT=0. I only see dcbtls used in
> start.S and no referendce to dcbtstls at all. I will consult the design
> team to confirm if the second step.
>

I got feedback from our design team. The second step is a must if these 
instructions are used. However, we don't hit either in U-Boot. Please be 
advised, if you have other code using dcbtls or dcbtstls with CT=0, you 
need to implement the 2nd step, i.e. proceed with a sync instruction.

York