[U-Boot] [PATCH 01/11] ARM: uniphier: enable SSC for more PLLs for LD20 SoC

[Masahiro Yamada]

For Electro-Magnetic Compatibility.

Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent.

Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>
---

 arch/arm/mach-uniphier/clk/dpll-ld20.c |  9 +++------
 arch/arm/mach-uniphier/clk/pll-ld20.c  | 15 ++++++++-------
 2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c
index 1132313..86e99c4 100644
--- a/arch/arm/mach-uniphier/clk/dpll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c
@@ -11,12 +11,9 @@
 
 int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
 {
-	unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
-	unsigned int dram_freq = bd->dram_freq;
-
-	uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
-	uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
-	uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
+	uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+	uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
 
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
index 5e545da..8ad6883 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -13,8 +13,6 @@
 
 int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
 {
-	unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
-
 	uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
 	/* do nothing for SPLL */
 	uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
@@ -24,11 +22,14 @@ int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
 
 	mdelay(1);
 
-	if (dpll_ssc_rate > 0) {
-		uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
-		uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
-		uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
-	}
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
 
 	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
 	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
-- 
1.9.1