[U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

[Marek Vasut]

On 10/29/2016 07:47 PM, Tom Rini wrote:
> On Sat, Oct 29, 2016 at 07:44:34PM +0200, Marek Vasut wrote:
>> On 10/29/2016 07:41 PM, Tom Rini wrote:
>>> On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:
>>>
>>>> While we setup the mmu initially we mark set_section_dcache with
>>>> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
>>>> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
>>>> 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
>>>> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
>>>> keeps all the regions execute okay and this leads to random speculative
>>>> fetches in random memory regions which was eventually caught by kernel
>>>> omap-l3-noc driver.
>>>>
>>>> Fix this to mark the regions as XN by default.
>>>>
>>>> Signed-off-by: Keerthy <j-keerthy at ti.com>
>>>> Reviewed-by: Alexander Graf <agraf at suse.de>
>>>
>>> Reviewed-by: Tom Rini <trini at konsulko.com>
>>>
>> Isn't this patch exactly undoing the following one ?
>>
>> commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
>> Author: Marek Vasut <>
>> Date:   Tue Dec 29 19:44:02 2015 +0100
>>
>>     arm: Remove S bit from MMU section entry
>>
>>     Restore the old behavior of the MMU section entries configuration,
>>     which is without the S-bit.
> 
> Is it?  I guess perhaps you and Keerthy need to chat then as there's
> some other problem they're addressing.

Ummmm, wait a second, I think this one adds XN bit and the previous one
removed S bit. I think I was wrong, but please double-check this. I
recall we had some odd cache issues on V7 back then.

-- 
Best regards,
Marek Vasut