[U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation
Jagan Teki
jagan at openedev.com
Mon Oct 31 10:24:47 CET 2016
On Mon, Oct 31, 2016 at 9:40 AM, Vignesh R <vigneshr at ti.com> wrote:
> Fix the divider calculation logic to choose a value so that the
> resulting baudrate is either equal to or closest possible baudrate less
> than the requested value. While at that, cleanup ti_spi_set_speed().
>
> Signed-off-by: Vignesh R <vigneshr at ti.com>
> ---
>
> v2: cleanup ti_spi_set_speed() a bit.
>
> drivers/spi/ti_qspi.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index 52520dff6325..b5de70bf40e3 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -16,6 +16,7 @@
> #include <asm/omap_gpio.h>
> #include <asm/omap_common.h>
> #include <asm/ti-common/ti-edma3.h>
> +#include <linux/kernel.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
> if (!hz)
> clk_div = 0;
> else
> - clk_div = (priv->fclk / hz) - 1;
> -
> - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
> + clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
>
> /* disable SCLK */
> writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
> &priv->base->clk_ctrl);
Move this before enable SCLK.
>
> - /* assign clk_div values */
> - if (clk_div < 0)
> - clk_div = 0;
> - else if (clk_div > QSPI_CLK_DIV_MAX)
> + /* truncate clk_div value to QSPI_CLK_DIV_MAX */
> + if (clk_div > QSPI_CLK_DIV_MAX)
> clk_div = QSPI_CLK_DIV_MAX;
>
> - /* enable SCLK */
> + debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
> +
> + /* enable SCLK and program the clk divider */
> writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
> }
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
More information about the U-Boot
mailing list