[U-Boot] [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[york sun]

On 10/30/2016 07:10 PM, Wenbin Song wrote:
> Hi york:
>
>
> Best Regards
> Wenbin Song
>
>> -----Original Message-----
>> From: york sun
>> Sent: Friday, October 28, 2016 11:40 PM
>> To: Wenbin Song <wenbin.song at nxp.com>; albert.u.boot at aribaud.net;
>> Mingkai Hu <mingkai.hu at nxp.com>; u-boot at lists.denx.de
>> Subject: Re: [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
>> node
>>
>> On 10/27/2016 02:06 AM, Wenbin song wrote:
>>> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
>>> alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
>>> is used to choose which offset will be used. If GIC_ADDR_BIT bit is
>>> set, 4K alignment is used, or else 64K alignment is used. The rev1.0
>>> silicon only supports the CIG offset with 4K alignment.
>>>
>>> GIC offset is decided by SVR and GIC_ADDR_BIT bit.
>>>
>>> Overriding the weak smp_kick_all_cpus, the new impletment is able to
>>> detect GIC offset.
>>>
>>> Signed-off-by: Wenbin Song <wenbin.song at nxp.com>
>>> Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
>>> ---
>>> Changes in v5:
>>> 	Replace fix_gic_off with get_gic_off.
>>> 	Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on
>> smp_kick_all_cpus.
>>> 	Fixup gic node with 64K alignment when running on rev1.1 with
>> GIC_ADDR_BIT cleared.
>>> ---
>>
>> <snip>
>>
>>>
>>> +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN static void fdt_fixup_gic(void
>>> +*blob) {
>>> +	int offset, err;
>>> +	u64 reg[8];
>>> +	struct ccsr_gur __iomem *gur = (void
>> *)(CONFIG_SYS_FSL_GUTS_ADDR);
>>> +	unsigned int rev;
>>> +	struct ccsr_scfg __iomem *scfg = (void
>> *)CONFIG_SYS_FSL_SCFG_ADDR;
>>> +	int align_4k = 1;
>>> +
>>> +	rev = gur_in32(&gur->svr) & 0xff;
>>> +
>>> +	if (rev > REV1_0) {
>>> +		rev = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
>>> +		if (!rev)
>>> +			align_4k = 0;
>>> +	}
>>> +
>>
>> Does this register scfg->gic_align exist for other SoCs? Can you get a consistent
>> reading from this register if not set by PBI? If yes, can you revert the logic in PBI
>> command to set this bit in backward compatible way?
>
>
> []  scfg->gic_align  is a new added  register on ls1043a rev1.1 or more higher  to select the GIC offset by PBI.
> If it is set by PBI,  GIC offset is 4K alignment.
> If it is cleared by PBI, GIC offset is 64K alignment.
> The reset value is cleared.
>
> So for ls1043a rev1.1 or more higher , we are be able to select the GIC offset  by using different rcw.
> If  not set by PBI, reading from it always gets  0.
>
>  And the scfg->gic_align is reserved for other SoCs.

So it is hard-wired to 0 for 64K. Keep you code to check the revision 
then. Maybe put a comment around checking the revision to warn later use 
for other SoCs?

York