[U-Boot] [PATCH 1/2] Add support for Turing Computer i.MX53 Evaluation Board
Mauricio Cirelli
mauricio at turingcomputer.com.br
Tue Apr 4 19:32:21 UTC 2017
Turing Computer is a designer and manufacturer of ARM-based
System on Modules, specialized on i.MX SoCs from Freescale/NXP.
This patch adds support for their Evaluation Board running i.MX53 SoC.
More information can be found at:
http://www.turingcomputer.com.br/
Signed-off-by: Mauricio Cirelli <mauricio at turingcomputer.com.br>
---
arch/arm/Kconfig | 7 +
board/turing/mx53turing/Kconfig | 15 ++
board/turing/mx53turing/MAINTAINERS | 6 +
board/turing/mx53turing/Makefile | 8 +
board/turing/mx53turing/imximage.cfg | 83 ++++++++
board/turing/mx53turing/mx53turing.c | 357 +++++++++++++++++++++++++++++++++++
configs/mx53turing_defconfig | 25 +++
include/configs/mx53turing.h | 212 +++++++++++++++++++++
8 files changed, 713 insertions(+)
create mode 100644 board/turing/mx53turing/Kconfig
create mode 100644 board/turing/mx53turing/MAINTAINERS
create mode 100644 board/turing/mx53turing/Makefile
create mode 100644 board/turing/mx53turing/imximage.cfg
create mode 100644 board/turing/mx53turing/mx53turing.c
create mode 100644 configs/mx53turing_defconfig
create mode 100644 include/configs/mx53turing.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b758745..49cc700 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -661,6 +661,12 @@ config TARGET_MX53SMD
select CPU_V7
select BOARD_EARLY_INIT_F
+config TARGET_MX53TURING
+ bool "Support Turing i.MX53 Boards"
+ select BOARD_LATE_INIT
+ select CPU_V7
+ select BOARD_EARLY_INIT_F
+
config OMAP34XX
bool "OMAP34XX SoC"
select ARCH_OMAP2
@@ -1268,6 +1274,7 @@ source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
+source "board/turing/mx53turing/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
diff --git a/board/turing/mx53turing/Kconfig b/board/turing/mx53turing/Kconfig
new file mode 100644
index 0000000..8984e15
--- /dev/null
+++ b/board/turing/mx53turing/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX53TURING
+
+config SYS_BOARD
+ default "mx53turing"
+
+config SYS_VENDOR
+ default "turing"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx53turing"
+
+endif
diff --git a/board/turing/mx53turing/MAINTAINERS b/board/turing/mx53turing/MAINTAINERS
new file mode 100644
index 0000000..c98e336
--- /dev/null
+++ b/board/turing/mx53turing/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53TURING BOARD
+M: Mauricio Cirelli <mauricio at turingcomputer.com.br>
+S: Maintained
+F: board/turing/mx53turing/
+F: include/configs/mx53turing.h
+F: configs/mx53turing_defconfig
diff --git a/board/turing/mx53turing/Makefile b/board/turing/mx53turing/Makefile
new file mode 100644
index 0000000..1f15c46
--- /dev/null
+++ b/board/turing/mx53turing/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2015 Turing Computer.
+# Mauricio Cirelli <mauricio at turingcomputer.com.br>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mx53turing.o
diff --git a/board/turing/mx53turing/imximage.cfg b/board/turing/mx53turing/imximage.cfg
new file mode 100644
index 0000000..27fb2cd
--- /dev/null
+++ b/board/turing/mx53turing/imximage.cfg
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015 Turing Computer.
+ * Mauricio Cirelli <mauricio at turingcomputer.com.br>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/turing/mx53turing/mx53turing.c b/board/turing/mx53turing/mx53turing.c
new file mode 100644
index 0000000..9edd4bc
--- /dev/null
+++ b/board/turing/mx53turing/mx53turing.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2015 Turing Computer.
+ * Mauricio Cirelli <mauricio at turingcomputer.com.br>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <linux/errno.h>
+#include <asm/imx-common/mx5_video.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
+}
+
+u32 get_board_rev(void)
+{
+ /* CPU Rev.D */
+ if (i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+ return 0;
+
+ /* CPU Rev.B */
+ return 1;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__UART5_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL1__UART5_TXD_MUX, UART_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__UART3_TXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__UART3_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__UART3_CTS, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__UART3_RTS, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_7__GPIO1_7);
+ gpio_direction_input(IMX_GPIO_NR(1, 7));
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 7));
+ else
+ ret = 1; /* Always present */
+
+ return ret;
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(sd2_pads, ARRAY_SIZE(sd2_pads));
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller (%d) as supported by the board (2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+}
+
+static int power_init(void)
+{
+ unsigned int val;
+ int ret;
+ int retries = 10;
+ struct pmic *p;
+
+ if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+ ret = pmic_dialog_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("DIALOG_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ setenv("fdt_file", "imx53-turing-da9053-eval.dtb");
+
+ /* Increase VDDGP as 1.25V for 1GHZ */
+ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+ do {
+ if (pmic_reg_write(p, DA9053_BUCKCORE_REG, val)) {
+ printf("da9052_i2c_is_connected - i2c write failed.....\n");
+ } else {
+ printf("da9052_i2c_is_connected - i2c write success....\n");
+ ret = 0;
+ }
+ } while (ret != 0 && retries--);
+
+ pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+ val |= DA9052_SUPPLY_VBCOREGO;
+ ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+ if (ret) {
+ printf("Writing to SUPPLY_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ /* restore VUSB_2V5 when reset from suspend state */
+ val = 0x55;
+ ret = pmic_reg_write(p, DA9053_ID1213_REG, val);
+ if (ret) {
+ printf("Writing to ID1213_REG failed: %d\n", ret);
+ return ret;
+ }
+ pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+ val |= 0x20;
+ ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+
+ return ret;
+ }
+
+ if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ setenv("fdt_file", "imx53-turing-mc34708-eval.dtb");
+
+ /* Set VDDGP to 1.25V for 1GHz on SW1 */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+ ret = pmic_reg_write(p, REG_SW_0, val);
+ if (ret) {
+ printf("Writing to REG_SW_0 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set VCC as 1.30V on SW2 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+ ret = pmic_reg_write(p, REG_SW_1, val);
+ if (ret) {
+ printf("Writing to REG_SW_1 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set global reset timer to 4s */
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
+ val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+ ret = pmic_reg_write(p, REG_POWER_CTL2, val);
+ if (ret) {
+ printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set VUSBSEL and VUSBEN for USB PHY supply*/
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+ ret = pmic_reg_write(p, REG_MODE_0, val);
+ if (ret) {
+ printf("Writing to REG_MODE_0 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set SWBST to 5V in auto mode */
+ val = SWBST_AUTO;
+ ret = pmic_reg_write(p, SWBST_CTRL, val);
+ if (ret) {
+ printf("Writing to SWBST_CTRL failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+ }
+
+ return -1;
+}
+
+static void clock_1GHz(void)
+{
+ int ret;
+ u32 ref_clk = MXC_HCLK;
+ /*
+ * After increasing voltage to 1.25V, we can switch
+ * CPU clock to 1GHz and DDR to 400MHz safely
+ */
+ ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to 1GHZ failed\n");
+
+ ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+ ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ setup_iomux_i2c();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ int ret = -1;
+ ret = power_init();
+
+ if (ret)
+ return ret;
+
+ clock_1GHz();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX53 TURING\n");
+
+ return 0;
+}
diff --git a/configs/mx53turing_defconfig b/configs/mx53turing_defconfig
new file mode 100644
index 0000000..f0ed71d
--- /dev/null
+++ b/configs/mx53turing_defconfig
@@ -0,0 +1,25 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MX53TURING=y
+CONFIG_VIDEO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/turing/mx53turing/imximage.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mx53turing.h b/include/configs/mx53turing.h
new file mode 100644
index 0000000..8d9a2e7
--- /dev/null
+++ b/include/configs/mx53turing.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343 at freescale.com>
+ *
+ * Configuration settings for Freescale MX53 low cost board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX53
+
+#define CONFIG_MACH_TYPE MACH_TYPE_MX53_TURING
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+#define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART5_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+/* Eth Configs */
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1F
+
+/* USB Configs */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_DIALOG_POWER
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ETHPRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE 0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "fdt_addr=0x71000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "hdmi_XGA=setenv bootargs ${bootargs} di1_primary video=mxcdi1fb:RGB24,1024x768M at 60 hdmi\0" \
+ "hdmi_720p=setenv bootargs ${bootargs} di1_primary video=mxcdi1fb:RGB24,1280x720M at 60 hdmi\0" \
+ "hdmi_1080p=setenv bootargs ${bootargs} di1_primary video=mxcdi1fb:RGB24,1080P60 hdmi\0" \
+ "lvds=setenv bootargs ${bootargs} di0_primary video=mxcdi0fb:RGB565,CLAA-WVGA ldb=di0 calibration\0" \
+ "dual_display=setenv bootargs ${bootargs} di0_primary video=mxcdi0fb:RGB565,CLAA-WVGA ldb=di0 calibration video=mxcdi1fb:RGB24,1024x768M at 60 hdmi\0" \
+ "set_display=run hdmi_XGA\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+ "mmcargs=setenv bootargs console=ttymxc4,${baudrate} root=${mmcroot} no_console_suspend\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "run set_display;" \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=ttymxc4,${baudrate} no_console_suspend\0" \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "run set_display;" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo ERROR: Cannot load the DT; " \
+ "exit; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE (gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 200000000
+
+
+#endif /* __CONFIG_H */
--
2.8.1
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