[U-Boot] [PATCH v4 23/35] ARM: i.MX6DL: sabresd: Move DCD reginit on SPL

[Jagan Teki]

From: Jagan Teki <jagan at amarulasolutions.com>

DCD register initialization from mx6dlsabresd.cfg are moved to
SPL code in mx6dl_dcd_table.

Now mx6sabresd SPL code support Dual Lite, Quad, Quad Plus.

mx6dl_dcd_table reginit as
- GPR io regs
- DRAM io regs,
- MMDC Calibration io regs
- dram sdcke0 (0x020e04a4) and sdcke1(0x020e04a8) are not available
  in original mx6dlsabresd.cfg but initialized to default values.

Cc: Stefano Babic <sbabic at denx.de>
Cc: Fabio Estevam <fabio.estevam at nxp.com>
Cc: Michael Trimarchi <michael at amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
Changes for v4:
- none
Changes for v3:
- Newly added
Changes for v2:
- none

 board/freescale/mx6sabresd/mx6sabresd.c | 64 ++++++++++++++++++++++++++++++++-
 1 file changed, 63 insertions(+), 1 deletion(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 67fc192..5595c08 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -893,6 +893,66 @@ static void gpr_init(void)
 	}
 }
 
+static int mx6dl_dcd_table[] = {
+	/* GPR io regs */
+	0x020e0774, 0x000C0000,
+	0x020e076c, 0x00000030,
+	0x020e0760, 0x00020000,
+	0x020e0754, 0x00000000,
+	0x020e0750, 0x00020000,
+	0x020e074c, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0784, 0x00000030,
+	0x020e0780, 0x00000030,
+	0x020e077c, 0x00000030,
+	0x020e0778, 0x00000030,
+	0x020e0770, 0x00000030,
+	0x020e0764, 0x00000030,
+
+	/* DRAM io regs */
+	0x020e04ac, 0x00000030,
+	0x020e04b0, 0x00000030,
+	0x020e0464, 0x00000030,
+	0x020e0490, 0x00000030,
+	0x020e0494, 0x00000030,
+	0x020e04a4, 0x00000030,
+	0x020e04a8, 0x00000030,
+	0x020e04a0, 0x00000000,
+	0x020e04b4, 0x00000030,
+	0x020e04b8, 0x00000030,
+	0x020e04bc, 0x00000030,
+	0x020e04c0, 0x00000030,
+	0x020e04c4, 0x00000030,
+	0x020e04c8, 0x00000030,
+	0x020e04cc, 0x00000030,
+	0x020e04d0, 0x00000030,
+	0x020e04d4, 0x00000030,
+	0x020e04d8, 0x00000030,
+	0x020e0470, 0x00000030,
+	0x020e0474, 0x00000030,
+	0x020e0478, 0x00000030,
+	0x020e047c, 0x00000030,
+	0x020e0480, 0x00000030,
+	0x020e0484, 0x00000030,
+	0x020e0488, 0x00000030,
+	0x020e048c, 0x00000030,
+
+	/* MMDC Calibration io regs */
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x4220021F,
+	0x021b0840, 0x0207017E,
+	0x021b483c, 0x4201020C,
+	0x021b4840, 0x01660172,
+	0x021b0848, 0x4A4D4E4D,
+	0x021b0850, 0x3F3C3D31,
+	0x021b4848, 0x4A4F5049,
+	0x021b4850, 0x3238372B,
+};
+
 static int mx6q_dcd_table[] = {
 	0x020e0798, 0x000C0000,
 	0x020e0758, 0x00000000,
@@ -1085,7 +1145,9 @@ static void ddr_init(int *table, int size)
 
 static void spl_dram_init(void)
 {
-	if (is_mx6dq())
+	if (is_mx6dl())
+		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+	else if (is_mx6dq())
 		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
 	else if (is_mx6dqp())
 		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
-- 
1.9.1