[U-Boot] [PATCH v2 1/8] rockchip: video: Add mipi dsi driver for rk3399
Eddie Cai
eddie.cai.linux at gmail.com
Tue Apr 18 14:15:26 UTC 2017
Hi Eric
2017-04-18 15:09 GMT+08:00 Eric Gao <eric.gao at rock-chips.com>:
> Signed-off-by: Eric Gao <eric.gao at rock-chips.com>
> ---
>
> Changes in v2:
> -Add mipi driver and it's header file
> -Add Kconfig and Makefile additions for mipi driver.
> -Add necessary Grf declaration for mipi driver.
>
> arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 25 ++
> arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 195 +++++++++
> drivers/video/rockchip/Kconfig | 11 +-
> drivers/video/rockchip/Makefile | 1 +
> drivers/video/rockchip/rk_mipi.c | 484
> +++++++++++++++++++++++
> 5 files changed, 714 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
> create mode 100644 drivers/video/rockchip/rk_mipi.c
>
> Can you split this patch into 4 patches. other comment as below.
1. grf changes
2. mipi driver
3. makefile change
4. kconfig
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> index b340b05..b4ba436 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> @@ -440,6 +440,31 @@ enum {
> GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
> GRF_UART_DBG_SEL_C = 2,
>
> + /* GRF_SOC_CON20 */
> + GRF_DSI0_VOP_SEL_SHIFT = 0,
> + GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT,
> + GRF_DSI0_VOP_SEL_B = 0,
> + GRF_DSI0_VOP_SEL_L,
> +
> + /* GRF_SOC_CON22 */
> + GRF_DPHY_TX0_RXMODE_SHIFT = 0,
> + GRF_DPHY_TX0_RXMODE_MASK =
> + 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
> + GRF_DPHY_TX0_RXMODE_EN = 0xb,
> + GRF_DPHY_TX0_RXMODE_DIS = 0,
> +
> + GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
> + GRF_DPHY_TX0_TXSTOPMODE_MASK =
> + 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
> + GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
> + GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
> +
> + GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
> + GRF_DPHY_TX0_TURNREQUEST_MASK =
> + 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
> + GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
> + GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
> +
>
alphabetical order please
> /* PMUGRF_GPIO0A_IOMUX */
> PMUGRF_GPIO0A6_SEL_SHIFT = 12,
> PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
> diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
> b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
> new file mode 100644
> index 0000000..f55ffb6
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
> @@ -0,0 +1,195 @@
> +/*
> + * Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd
>
this year is 2017. so should be "Copyright (C) 2017 Fuzhou Rockchip
Electronics Co., Ltd"
> + * author: Eric Gao <eric.gao at rock-chips.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef RK33_MIPI_DSI_H
> +#define RK33_MIPI_DSI_H
>
this driver is not only for rk33. we may use it on rk32 or other chips. So
please use ROCKCHIP_MIPI_DSI_H
> +
> +/*
> + * All these mipi controller register declaration provide reg address
> offset,
> + * bits width, bit offset for a specified register bits. With these
> message, we
> + * can set or clear every bits individually for a 32bit widthregister. We
> use
> + * DSI_HOST_BITS macro definition to combinat these message using the
> following
> + * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
> + * For example:
> + * #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
> + * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's
> reg addr
> + * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0
> + */
> +#define ADDR_SHIFT 16
> +#define BITS_SHIFT 8
> +#define OFFSET_SHIFT 0
> +#define DSI_HOST_BITS(addr, bits, bit_offset) \
> +((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset <<
> OFFSET_SHIFT))
> +
> +/* DWC_DSI_VERSION_0x3133302A */
> +#define VERSION DSI_HOST_BITS(0x000, 32, 0)
> +#define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
> +#define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8)
> +#define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0)
> +#define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0)
> +#define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8)
> +#define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0)
> +#define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4)
> +#define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3)
> +#define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2)
> +#define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1)
> +#define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0)
> +#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16)
> +#define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0)
> +#define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4)
> +#define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3)
> +#define BTA_EN DSI_HOST_BITS(0x02c, 1, 2)
> +#define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1)
> +#define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0)
> +#define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0)
> +#define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0)
> +#define VPG_ORIENTATION DSI_HOST_BITS(0x038, 1, 24)
> +#define VPG_MODE DSI_HOST_BITS(0x038, 1, 20)
> +#define VPG_EN DSI_HOST_BITS(0x038, 1, 16)
> +#define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15)
> +#define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14)
> +#define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13)
> +#define LP_HBP_EN DSI_HOST_BITS(0x038, 1, 12)
> +#define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11)
> +#define LP_VFP_EN DSI_HOST_BITS(0x038, 1, 10)
> +#define LP_VBP_EN DSI_HOST_BITS(0x038, 1, 9)
> +#define LP_VSA_EN DSI_HOST_BITS(0x038, 1, 8)
> +#define VID_MODE_TYPE DSI_HOST_BITS(0x038, 2, 0)
> +#define VID_PKT_SIZE DSI_HOST_BITS(0x03c, 14, 0)
> +#define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0)
> +#define NULL_PKT_SIZE DSI_HOST_BITS(0x044, 13, 0)
> +#define VID_HSA_TIME DSI_HOST_BITS(0x048, 12, 0)
> +#define VID_HBP_TIME DSI_HOST_BITS(0x04c, 12, 0)
> +#define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0)
> +#define VID_VSA_LINES DSI_HOST_BITS(0x054, 10, 0)
> +#define VID_VBP_LINES DSI_HOST_BITS(0x058, 10, 0)
> +#define VID_VFP_LINES DSI_HOST_BITS(0x05c, 10, 0)
> +#define VID_ACTIVE_LINES DSI_HOST_BITS(0x060, 14, 0)
> +#define EDPI_CMD_SIZE DSI_HOST_BITS(0x064, 16, 0)
> +#define MAX_RD_PKT_SIZE DSI_HOST_BITS(0x068, 1, 24)
> +#define DCS_LW_TX DSI_HOST_BITS(0x068, 1, 19)
> +#define DCS_SR_0P_TX DSI_HOST_BITS(0x068, 1, 18)
> +#define DCS_SW_1P_TX DSI_HOST_BITS(0x068, 1, 17)
> +#define DCS_SW_0P_TX DSI_HOST_BITS(0x068, 1, 16)
> +#define GEN_LW_TX DSI_HOST_BITS(0x068, 1, 14)
> +#define GEN_SR_2P_TX DSI_HOST_BITS(0x068, 1, 13)
> +#define GEN_SR_1P_TX DSI_HOST_BITS(0x068, 1, 12)
> +#define GEN_SR_0P_TX DSI_HOST_BITS(0x068, 1, 11)
> +#define GEN_SW_2P_TX DSI_HOST_BITS(0x068, 1, 10)
> +#define GEN_SW_1P_TX DSI_HOST_BITS(0x068, 1, 9)
> +#define GEN_SW_0P_TX DSI_HOST_BITS(0x068, 1, 8)
> +#define ACK_RQST_EN DSI_HOST_BITS(0x068, 1, 1)
> +#define TEAR_FX_EN DSI_HOST_BITS(0x068, 1, 0)
> +#define GEN_WC_MSBYTE DSI_HOST_BITS(0x06c, 14, 16)
> +#define GEN_WC_LSBYTE DSI_HOST_BITS(0x06c, 8, 8)
> +#define GEN_VC DSI_HOST_BITS(0x06c, 2, 6)
> +#define GEN_DT DSI_HOST_BITS(0x06c, 6, 0)
> +#define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0)
> +#define GEN_RD_CMD_BUSY DSI_HOST_BITS(0x074, 1, 6)
> +#define GEN_PLD_R_FULL DSI_HOST_BITS(0x074, 1, 5)
> +#define GEN_PLD_R_EMPTY DSI_HOST_BITS(0x074, 1, 4)
> +#define GEN_PLD_W_FULL DSI_HOST_BITS(0x074, 1, 3)
> +#define GEN_PLD_W_EMPTY DSI_HOST_BITS(0x074, 1, 2)
> +#define GEN_CMD_FULL DSI_HOST_BITS(0x074, 1, 1)
> +#define GEN_CMD_EMPTY DSI_HOST_BITS(0x074, 1, 0)
> +#define HSTX_TO_CNT DSI_HOST_BITS(0x078, 16, 16)
> +#define LPRX_TO_CNT DSI_HOST_BITS(0x078, 16, 0)
> +#define HS_RD_TO_CNT DSI_HOST_BITS(0x07c, 16, 0)
> +#define LP_RD_TO_CNT DSI_HOST_BITS(0x080, 16, 0)
> +#define PRESP_TO_MODE DSI_HOST_BITS(0x084, 1, 24)
> +#define HS_WR_TO_CNT DSI_HOST_BITS(0x084, 16, 0)
> +#define LP_WR_TO_CNT DSI_HOST_BITS(0x088, 16, 0)
> +#define BTA_TO_CNT DSI_HOST_BITS(0x08c, 16, 0)
> +#define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0x094, 1, 1)
> +#define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0x094, 1, 0)
> +#define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 16)
> +#define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 0)
> +#define PHY_HS2LP_TIME DSI_HOST_BITS(0x09c, 8, 24)
> +#define PHY_LP2HS_TIME DSI_HOST_BITS(0x09c, 8, 16)
> +#define MAX_RD_TIME DSI_HOST_BITS(0x09c, 15, 0)
> +#define PHY_FORCEPLL DSI_HOST_BITS(0x0a0, 1, 3)
> +#define PHY_ENABLECLK DSI_HOST_BITS(0x0a0, 1, 2)
> +#define PHY_RSTZ DSI_HOST_BITS(0x0a0, 1, 1)
> +#define PHY_SHUTDOWNZ DSI_HOST_BITS(0x0a0, 1, 0)
> +#define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0x0a4, 8, 8)
> +#define N_LANES DSI_HOST_BITS(0x0a4, 2, 0)
> +#define PHY_TXEXITULPSLAN DSI_HOST_BITS(0x0a8, 1, 3)
> +#define PHY_TXREQULPSLAN DSI_HOST_BITS(0x0a8, 1, 2)
> +#define PHY_TXEXITULPSCLK DSI_HOST_BITS(0x0a8, 1, 1)
> +#define PHY_TXREQULPSCLK DSI_HOST_BITS(0x0a8, 1, 0)
> +#define PHY_TX_TRIGGERS DSI_HOST_BITS(0x0ac, 4, 0)
> +#define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0x0b0, 1, 2)
> +#define PHYLOCK DSI_HOST_BITS(0x0b0, 1, 0)
> +#define PHY_TESTCLK DSI_HOST_BITS(0x0b4, 1, 1)
> +#define PHY_TESTCLR DSI_HOST_BITS(0x0b4, 1, 0)
> +#define PHY_TESTEN DSI_HOST_BITS(0x0b8, 1, 16)
> +#define PHY_TESTDOUT DSI_HOST_BITS(0x0b8, 8, 8)
> +#define PHY_TESTDIN DSI_HOST_BITS(0x0b8, 8, 0)
> +#define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0)
> +#define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0)
> +#define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0)
> +#define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0)
> +#define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0)
> +#define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0)
> +#define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0)
> +#define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0)
> +
> +#define CODE_HS_RX_CLOCK 0x34
> +#define CODE_HS_RX_LANE0 0x44
> +#define CODE_HS_RX_LANE1 0x54
> +#define CODE_HS_RX_LANE2 0x84
> +#define CODE_HS_RX_LANE3 0x94
> +
> +#define CODE_PLL_VCORANGE_VCOCAP 0x10
> +#define CODE_PLL_CPCTRL 0x11
> +#define CODE_PLL_LPF_CP 0x12
> +#define CODE_PLL_INPUT_DIV_RAT 0x17
> +#define CODE_PLL_LOOP_DIV_RAT 0x18
> +#define CODE_PLL_INPUT_LOOP_DIV_RAT 0x19
> +#define CODE_BANDGAP_BIAS_CTRL 0x20
> +#define CODE_TERMINATION_CTRL 0x21
> +#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22
> +
> +#define CODE_HSTXDATALANEREQUSETSTATETIME 0x70
> +#define CODE_HSTXDATALANEPREPARESTATETIME 0x71
> +#define CODE_HSTXDATALANEHSZEROSTATETIME 0x72
> +
> +/* Transmission mode between vop and MIPI controller */
> +enum vid_mode_type_t {
> + NON_BURST_SYNC_PLUSE = 0,
> + NON_BURST_SYNC_EVENT,
> + BURST_MODE,
> +};
> +
> +enum cmd_video_mode {
> + VIDEO_MODE = 0,
> + CMD_MODE,
> +};
> +
> +/* Indicate MIPI DSI color mode */
> +enum dpi_color_coding {
> + DPI_16BIT_CFG_1 = 0,
> + DPI_16BIT_CFG_2,
> + DPI_16BIT_CFG_3,
> + DPI_18BIT_CFG_1,
> + DPI_18BIT_CFG_2,
> + DPI_24BIT,
> + DPI_20BIT_YCBCR_422_LP,
> + DPI_24BIT_YCBCR_422,
> + DPI_16BIT_YCBCR_422,
> + DPI_30BIT,
> + DPI_36BIT,
> + DPI_12BIT_YCBCR_420,
> +};
> +
> +/* Indicate which VOP the MIPI DSI use, bit or little one */
> +enum vop_id {
> + VOP_B = 0,
> + VOP_L,
> +};
> +
> +#endif /* end of RK33_MIPI_DSI_H */
> diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/
> Kconfig
> index 09c4ea2..3f57d5c 100644
> --- a/drivers/video/rockchip/Kconfig
> +++ b/drivers/video/rockchip/Kconfig
> @@ -37,7 +37,14 @@ if VIDEO_ROCKCHIP
> bool "HDMI port"
> depends on VIDEO_ROCKCHIP
> help
> - This enable High-Definition Multimedia Interface
> display support.
> + This enable High-Definition Multimedia
> Interface(HDMI) display
> + support.
>
> + config DISPLAY_MIPI
> + bool "MIPI Port"
> + depends on VIDEO_ROCKCHIP
> + help
> + This enables Mobile Industry Processor
> Interface(MIPI) display
> + support. The mipi controller and dphy on rk3288&
> rk3399 support
> + 16,18, 24 bits per pixel with upto 2k resolution
> ratio.
> endif
> -
> diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/
> Makefile
> index 3bb0519..f9d1abf 100644
> --- a/drivers/video/rockchip/Makefile
> +++ b/drivers/video/rockchip/Makefile
> @@ -10,4 +10,5 @@ obj-y += rk_vop.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o
> +obj-$(CONFIG_DISPLAY_MIPI) += rk_mipi.o
>
to follow the naming rule of other rockchip display driver. it should be
CONFIG_DISPLAY_ROCKCHIP_MIPI
> endif
> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_
> mipi.c
> new file mode 100644
> index 0000000..de59f65
> --- /dev/null
> +++ b/drivers/video/rockchip/rk_mipi.c
> @@ -0,0 +1,484 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>
2017 please
> + * Author: Eric Gao <eric.gao at rock-chips.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <display.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <panel.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/gpio.h>
> +#include <asm/hardware.h>
> +#include <asm/io.h>
> +#include <dm/uclass-internal.h>
> +#include <linux/kernel.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3399.h>
> +#include <asm/arch/grf_rk3399.h>
> +#include <asm/arch/mipi_rk3399.h>
> +#include <dt-bindings/clock/rk3288-cru.h>
>
alphabetical order please
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Private information for rk mipi
> + *
> + * @regs: mipi controller address
> + * @grf: GRF register
> + * @panel: panel assined by device tree
> + * @ref_clk: reference clock for mipi dsi pll
> + * @sysclk: config clock for mipi dsi register
> + * @pix_clk: pixel clock for vop->dsi data transmission
> + * @phy_clk: mipi dphy output clock
> + * @txbyte_clk: clock for dsi->dphy high speed data transmission
> + * @txesc_clk: clock for tx esc mode
> + */
> +struct rk_mipi_priv {
> + void __iomem *regs;
> + struct rk3399_grf_regs *grf;
> + struct udevice *panel;
> + struct mipi_dsi *dsi;
> + u32 ref_clk;
> + u32 sys_clk;
> + u32 pix_clk;
> + u32 phy_clk;
> + u32 txbyte_clk;
> + u32 txesc_clk;
> +};
> +
> +static int rk_mipi_read_timing(struct udevice *dev,
> + struct display_timing *timing)
> +{
> + if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
> + 0, timing)) {
> + debug("%s: Failed to decode display timing\n", __func__);
>
can you print the return value here if fdtdec_decode_display_timing failed?
> + return -EINVAL;
+ }
> +
> + return 0;
> +}
> +
> +/*
> + * Register write function used only for mipi dsi controller.
> + * Parameter:
> + * reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you
> can use
> + * define in rk_mipi.h directly for this parameter
> + * val: value that will be write to specified bits of register
>
lost the meaning of val
> + */
> +static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val)
> +{
> + u32 dat;
> + u32 mask;
> + u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
> + u32 bits = (reg >> BITS_SHIFT) & 0xff;
> + u64 addr = (reg >> ADDR_SHIFT) + regs;
> +
> + /* Mask for specifiled bits,the corresponding bits will be clear */
> + mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset -
> bits)));
> +
> + /* Make sure val in the available range */
> + val &= ~(0xffffffff << bits);
> +
> + /* Get register's original val */
> + dat = readl(addr);
> +
> + /* Clear specified bits */
> + dat &= mask;
> +
> + /* Fill specified bits */
> + dat |= val << offset;
> +
> + writel(dat, addr);
> +}
> +
> +static int rk_mipi_dsi_enable(struct udevice *dev,
> + const struct display_timing *timing)
> +{
> + int node, timing_node;
> + int val;
> + struct rk_mipi_priv *priv = dev_get_priv(dev);
> + u64 regs = (u64)priv->regs;
> + struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
> + u32 txbyte_clk = priv->txbyte_clk;
> + u32 txesc_clk = priv->txesc_clk;
> +
> + txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
> +
> + /* Select the video source */
> + switch (disp_uc_plat->source_id) {
> + case VOP_B:
> + rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
> + GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
> + break;
> + case VOP_L:
> + rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
> + GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
> + break;
> + default:
> + debug("%s: Invalid VOP id\n", __func__);
> + return -EINVAL;
> + }
> +
> + /* Set Controller as TX mode */
> + val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
> + rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK,
> val);
> +
> + /* Exit tx stop mode */
> + val |= GRF_DPHY_TX0_TXSTOPMODE_DIS <<
> GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
> + rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK,
> val);
> +
> + /* Disable turnequest */
> + val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_
> SHIFT;
> + rk_clrsetreg(&priv->grf->soc_con22,
> GRF_DPHY_TX0_TURNREQUEST_MASK, val);
> +
> + /* Set Display timing parameter */
> + rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
> + rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
> + rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
> + + timing->hback_porch.typ + timing->hactive.typ
> + + timing->hfront_porch.typ));
> + rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
> + rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
> + rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
> + rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
> +
> + /* Set Signal Polarity */
> + val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
> + rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
> +
> + val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
> + rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
> +
> + val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
> + rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val);
> +
> + val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
> + rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
> +
> + /* Set video mode */
> + rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
> +
> + /* Set video mode transmission type as burst mode */
> + rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
> +
> + /* Set pix num in a video package */
> + rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
> +
> + /* Set dpi color coding depth 24 bit */
> + timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
> +
> "display-timings");
> + node = fdt_first_subnode(gd->fdt_blob, timing_node);
> + val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
> + switch (val) {
> + case 16:
> + rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
> + break;
> + case 24:
> + rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
> + break;
> + case 30:
> + rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
> + break;
> + default:
> + rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
> + }
> + /* Enable low power mode */
> + rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
> + rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
> + rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
> + rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
> + rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
> + rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
> +
> + /* Division for timeout counter clk */
> + rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
> +
> + /* Tx esc clk division from txbyte clk */
> + rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
> +
> + /* Timeout count for hs<->lp transation between Line period */
> + rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
> +
> + /* Phy State transfer timing */
> + rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
> + rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
> + rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
> + rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
> + rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
> +
> + /* Power on */
> + rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
> +
> + return 0;
> +}
> +
> +/* rk mipi dphy write function. It is used to write test data to dphy */
> +static void rk_mipi_phy_write(u32 regs, unsigned char test_code,
> + unsigned char *test_data, unsigned char size)
> +{
> + int i = 0;
> +
> + /* Write Test code */
> + rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
> + rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
> + rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
> + rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
> + rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
> +
> + /* Write Test data */
> + for (i = 0; i < size; i++) {
> + rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
> + rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
> + rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
> + }
> +}
> +
> +/*
> + * Mipi dphy config function. Calculate the suitable prediv, feedback div,
> + * fsfreqrang value ,cap ,lpf and so on according to the given pix clk
> rate,
> + * and then enable phy.
> + */
> +static int rk_mipi_phy_enable(struct udevice *dev)
> +{
> + int i;
> + struct rk_mipi_priv *priv = dev_get_priv(dev);
> + u64 regs = (u64)priv->regs;
> + u64 fbdiv;
> + u64 prediv = 1;
> + u32 max_fbdiv = 512;
> + u32 max_prediv, min_prediv;
> + u64 ddr_clk = priv->phy_clk;
> + u32 refclk = priv->ref_clk;
> + u32 remain = refclk;
> + unsigned char test_data[2] = {0};
> +
> + int freq_rang[][2] = {
> + {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
> + {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
> + {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
> + {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
> + {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
> + {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
> + {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
> + {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
> + {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
> + {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
> + };
> +
> + /* Shutdown mode */
> + rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
> + rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
> + rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
> +
> + /* Pll locking */
> + rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
> +
> + /* config cp and lfp */
> + test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
> + rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
> +
> + test_data[0] = 0x8;
> + rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
> +
> + test_data[0] = 0x80 | 0x40;
> + rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
> +
> + /* select the suitable value for fsfreqrang reg */
> + for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
> + if (ddr_clk / (MHz) >= freq_rang[i][0])
> + break;
> + }
> + if (i == ARRAY_SIZE(freq_rang)) {
> + debug("%s: Dphy freq out of range!\n", __func__);
> + return -EINVAL;
> + }
> + test_data[0] = freq_rang[i][1] << 1;
> + rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
> +
> + /*
> + * Calculate the best ddrclk and it's corresponding div value. If
> the
> + * given pixelclock is great than 250M, ddrclk will be fix 1500M.
> + * Otherwise,
> + * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >=
> 5MHz
> + * according to spec.
> + */
> + max_prediv = (refclk / (5 * MHz));
> + min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) :
> 1);
> +
> + debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__,
> max_prediv,
> + min_prediv);
> +
> + if (max_prediv < min_prediv) {
> + debug("%s: Invalid refclk value\n", __func__);
> + return -EINVAL;
> + }
> +
> + /* Calculate the best refclk and feedback division value for dphy
> pll */
> + for (i = min_prediv; i < max_prediv; i++) {
> + if ((ddr_clk * i % refclk < remain) &&
> + (ddr_clk * i / refclk) < max_fbdiv) {
> + prediv = i;
> + remain = ddr_clk * i % refclk;
> + }
> + }
> + fbdiv = ddr_clk * prediv / refclk;
> + ddr_clk = refclk * fbdiv / prediv;
> + priv->phy_clk = ddr_clk;
> +
> + debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu,
> phyclk=%llu\n",
> + __func__, refclk, prediv, fbdiv, ddr_clk);
> +
> + /* config prediv and feedback reg */
> + test_data[0] = prediv - 1;
> + rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
> + test_data[0] = (fbdiv - 1) & 0x1f;
> + rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
> + test_data[0] = (fbdiv - 1) >> 5 | 0x80;
> + rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
> + test_data[0] = 0x30;
> + rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
> +
> + /* rest config */
> + test_data[0] = 0x4d;
> + rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
> +
> + test_data[0] = 0x3d;
> + rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
> +
> + test_data[0] = 0xdf;
> + rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
> +
> + test_data[0] = 0x7;
> + rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data,
> 1);
> +
> + test_data[0] = 0x80 | 0x7;
> + rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data,
> 1);
> +
> + test_data[0] = 0x80 | 15;
> + rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
> + test_data, 1);
> + test_data[0] = 0x80 | 85;
> + rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
> + test_data, 1);
> + test_data[0] = 0x40 | 10;
> + rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
> + test_data, 1);
> +
> + /* enter into stop mode */
> + rk_mipi_dsi_write(regs, N_LANES, 0x03);
> + rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
> + rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
> + rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
> + rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
> +
> + return 0;
> +}
> +
> +/*
> + * This function is called by rk_display_init() using
> rk_mipi_dsi_enable() and
> + * rk_mipi_phy_enable() to initialize mipi controller and dphy. If
> success,
> + * enable backlight.
> + */
> +static int rk_display_enable(struct udevice *dev, int panel_bpp,
> + const struct display_timing *timing)
> +{
> + int ret;
> + struct rk_mipi_priv *priv = dev_get_priv(dev);
> +
> + /* Fill the mipi controller parameter */
> + priv->ref_clk = 24 * MHz;
> + priv->sys_clk = priv->ref_clk;
> + priv->pix_clk = timing->pixelclock.typ;
> + priv->phy_clk = priv->pix_clk * 6;
> + priv->txbyte_clk = priv->phy_clk / 8;
> + priv->txesc_clk = 20 * MHz;
> +
> + /* Config and enable mipi dsi according to timing */
> + ret = rk_mipi_dsi_enable(dev, timing);
> + if (ret) {
> + debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
> + __func__, ret);
> + return ret;
> + }
> +
> + /* Config and enable mipi phy */
> + ret = rk_mipi_phy_enable(dev);
> + if (ret) {
> + debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
> + __func__, ret);
> + return ret;
> + }
> +
> + /* Enable backlight */
> + ret = panel_enable_backlight(priv->panel);
> + if (ret) {
> + debug("%s: panel_enable_backlight() failed (err=%d)\n",
> + __func__, ret);
> + return ret;
> + }
+
> + return 0;
> +}
> +
> +static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk_mipi_priv *priv = dev_get_priv(dev);
> +
> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (!priv->grf) {
> + debug("%s: Get syscon grf failed\n", __func__);
>
can you print the return value from syscon_get_first_range?
> + return -ENXIO;
> + }
> + priv->regs = (void *)dev_get_addr(dev);
> + if (!priv->regs) {
> + debug("%s: Get MIPI dsi address failed\n", __func__);
>
can you print the return value from dev_get_addr?
> + return -ENXIO;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Probe function: check panel existence and readingit's timing. Then
> config
> + * mipi dsi controller and enable it according to the timing parameter.
> + */
> +static int rk_mipi_probe(struct udevice *dev)
> +{
> + int ret;
> + struct rk_mipi_priv *priv = dev_get_priv(dev);
> +
> + ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
> "rockchip,panel",
> + &priv->panel);
> + if (ret) {
> + debug("%s: Can not find panel (err=%d)\n", __func__, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct dm_display_ops rk_mipi_dsi_ops = {
> + .read_timing = rk_mipi_read_timing,
> + .enable = rk_display_enable,
> +};
> +
> +static const struct udevice_id rk_mipi_dsi_ids[] = {
> + { .compatible = "rockchip,rk3399_mipi_dsi" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rk_mipi_dsi) = {
> + .name = "rk_mipi_dsi",
> + .id = UCLASS_DISPLAY,
> + .of_match = rk_mipi_dsi_ids,
> + .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
> + .probe = rk_mipi_probe,
> + .ops = &rk_mipi_dsi_ops,
> + .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
> +};
> --
> 1.9.1
>
>
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