[U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > 
> > Really including Dalon
> > 
> > > 
> > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen at kernel.org> wrote:
> > > CC: Dalon Westergreen
> > > 
> > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > 
> > > > 
> > > > 
> > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > 
> > > > > Add SPL support for Arria 10.
> > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> > > > > > > > > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com>
> > > > > ---
> > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > >  arch/arm/mach-socfpga/spl.c | 72
> +++++++++++++++++++++++++++++++++++++++++----
> > 
> > > 
> > > > 
> > > > > 
> > > > >  1 file changed, 67 insertions(+), 5 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> > > > > index 0064fc8..f4a3cdd 100644
> > > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > > @@ -19,23 +19,32 @@
> > > > >  #include <asm/arch/sdram.h>
> > > > >  #include <asm/arch/scu.h>
> > > > >  #include <asm/arch/nic301.h>
> > > > > +#include <asm/sections.h>
> > > > > +#include <fdtdec.h>
> > > > > +#include <watchdog.h>
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > +#include <asm/arch/pinmux.h>
> > > > > +#endif
> > > > > 
> > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > 
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > >  static struct pl310_regs *const pl310 =
> > > > >      (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > >  static struct scu_registers *scu_regs =
> > > > >      (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > > > >  static struct nic301_registers *nic301_regs =
> > > > >      (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > > > > -static struct socfpga_system_manager *sysmgr_regs =
> > > > > +#endif
> > > > > +
> > > > > +static const struct socfpga_system_manager *sysmgr_regs =
> > > > >      (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > > > > 
> > > > >  u32 spl_boot_device(void)
> > > > >  {
> > > > >      const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > > > > 
> > > > > -    switch (bsel & 0x7) {
> > > > > +    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > > > >      case 0x1:       /* FPGA (HPS2FPGA Bridge) */
> > > > >              return BOOT_DEVICE_RAM;
> > > > >      case 0x2:       /* NAND Flash (1.8V) */
> > > > > @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
> > > > >  }
> > > > >  #endif
> > > > > 
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > >  static void socfpga_nic301_slave_ns(void)
> > > > >  {
> > > > >      writel(0x1, &nic301_regs->lwhps2fpgaregs);
> > > > > @@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
> > > > >  #endif
> > > > >      unsigned long sdram_size;
> > > > >      unsigned long reg;
> > > > > +    int ret;
> > > > > 
> > > > >      /*
> > > > >       * First C code to run. Clear fake OCRAM ECC first as SBE
> > > > > @@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
> > > > >      /* Put everything into reset but L4WD0. */
> > > > >      socfpga_per_reset_all();
> > > > >      /* Put FPGA bridges into reset too. */
> > > > > -    socfpga_bridges_reset(1);
> > > > > +    ret = socfpga_bridges_reset(1);
> > > > > +    if (ret) {
> > > > > +            printf("socfpga_bridges_reset() failed: %d\n", ret);
> > > > > +            hang();
> > > > > +    }
> > > > > 
> > > > >      socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> > > > >      socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> > > > > @@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
> > > > > 
> > > > >      /* De-assert reset for peripherals and bridges based on handoff
> > > > > */
> > > > >      reset_deassert_peripherals_handoff();
> > > > > -    socfpga_bridges_reset(0);
> > > > > +    ret = socfpga_bridges_reset(0);
> > > > > +    if (ret) {
> > > > > +            printf("socfpga_bridges_reset() failed: %d\n", ret);
> > > > > +            hang();
> > > > 
> > > > If you keep this patch the way it is, this will cause the Atlas board to
> > > > hang here.
> > > > 
> > > 
> > > Hi Dalon,
> > > 
> > > Can you check this patch? On the Atlas board, I'm seeing the call to
> > > socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is
> > > failing, because is_fpgamgr_initdone_high() is returning 0.
> > > 
> > > Dinh
> 
> i saw it the first go round.  i will test this out this afternoon.
> 
> --dalon

i see the exact same thing.  for the c5/a5 devices there is no reason for init
done to be high since fpga configuration isnt required to boot. 

--dalon

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