[U-Boot] [PATCH 1/2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support
Priyanka Jain
priyanka.jain at nxp.com
Sat Apr 22 09:38:06 UTC 2017
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and
is built on layerscape architecture.
It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A).
So feature-wise it is same as LS2084A.
LS2081A has one more similar personality which
has four CPUs: LS2041A
Signed-off-by: Priyanka Jain <priyanka.jain at nxp.com>
Signed-off-by: Santan Kumar <santan.kumar at nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 ++-
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 11 +++++++++++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
drivers/pci/pcie_layerscape.c | 6 ++++--
drivers/pci/pcie_layerscape.h | 2 ++
drivers/pci/pcie_layerscape_fixup.c | 6 ++++--
7 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c24f3f1..6e46257 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -102,7 +102,8 @@ static void fix_pcie_mmu_map(void)
/* Fix PCIE base and size for LS2088A */
if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
- (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+ (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
+ (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
for (i = 0; i < ARRAY_SIZE(final_map); i++) {
switch (final_map[i].phys) {
case CONFIG_SYS_PCIE1_PHYS_ADDR:
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index c7496c0..3ae16ae 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -5,6 +5,7 @@ SoC overview
3. LS1012A
4. LS1046A
5. LS2088A
+ 6. LS2081A
LS1043A
---------
@@ -227,3 +228,13 @@ LS2088A SoC has 3 more similar SoC personalities
3)LS2044A, few difference w.r.t. LS2084A:
a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+LS2081A
+--------
+LS2081A is 40-pin derivative of LS2084A.
+So feature-wise it is same as LS2084A.
+Refer to LS2084A(LS2088A) section above for details.
+
+It has one more similar SoC personality
+1)LS2041A, few difference w.r.t. LS2081A:
+ a) Four 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 95c3e2f..9086aba 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -15,6 +15,8 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+ CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+ CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 426fe8e..5f3b19f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -54,6 +54,8 @@ struct cpu_type {
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
+#define SVR_LS2081A 0x870919
+#define SVR_LS2041A 0x870915
#define SVR_DEV_LS2080A 0x8701
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 1c5a33a..dcd9632 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -170,7 +170,8 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
/* Fix the pcie memory map for LS2088A series SoCs */
svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A) {
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A) {
if (io)
io->phys_start = (io->phys_start &
(PCIE_PHYS_SIZE - 1)) +
@@ -531,7 +532,8 @@ static int ls_pcie_probe(struct udevice *dev)
svr = get_svr();
svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A) {
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A) {
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie->ctrl = pcie->lut + 0x40000;
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index e3324a5..100a6c9 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -117,6 +117,8 @@
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
+#define SVR_LS2081A 0x870919
+#define SVR_LS2041A 0x870915
/* LS1021a PCIE space */
#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index d504bbd..88a3ba2 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -82,7 +82,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A)
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A)
compat = "fsl,ls2088a-pcie";
else
compat = CONFIG_FSL_PCIE_COMPAT;
@@ -217,7 +218,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
- svr == SVR_LS2048A || svr == SVR_LS2044A)
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A)
compat = "fsl,ls2088a-pcie";
else
compat = CONFIG_FSL_PCIE_COMPAT;
--
1.7.4.1
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