[U-Boot] [EXT] Armada 385: PEX detection pulse width

[Rene Straub]

Hello Adam,

first of all thanks the quick reply. First trials with reduced pulse length, showed promising results. To better understand the root cause of the problem, it would be helpful if you explained us briefly what the register change actually performs. I/we understand that the problem is related to the process of Rx Detection (measuring voltage change on PCIe link after a common mode step). Maybe we can implement a board change (PCIe lane coupling capacitors) to improve the detection, even with the default pulse length of the A385.

Best regards
-Rene


-----Original Message-----
From: Adam Shobash [mailto:adams at marvell.com] 
Sent: Sonntag, 23. April 2017 19:29
To: Stefan Eichenberger <Stefan.Eichenberger at netmodule.com>
Cc: Assaf Hoffman <hoffman at marvell.com>; Rene Straub <Rene.Straub at netmodule.com>; sr at denx.de; u-boot at lists.denx.de
Subject: RE: [EXT] Armada 385: PEX detection pulse width

Hi Stefan,

In A385, the register to change the pulse width is 0xa0120 bits[7:6].
Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see if it solves the issue.

But, please note that we tested our platforms with the value 0x1 only and we cannot guarantee that after you change this value that it will work for all the devices/add in cards other than Atheros .

Thanks,
Adam

-----Original Message-----
From: Stefan Eichenberger [mailto:stefan.eichenberger at netmodule.com] 
Sent: Friday, April 21, 2017 11:51 AM
To: Adam Shobash
Cc: Assaf Hoffman; René Straub; sr at denx.de; u-boot at lists.denx.de
Subject: [EXT] Armada 385: PEX detection pulse width

External Email

----------------------------------------------------------------------
Dear Adam,

On the mainline u-boot we found a commit which helps to fix a problem regarding PCIe and the Armada 370:
http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0251f2aea

We currently facing a similar problem with the Armada 385 and PCIe. The problem also appears with two different Atheros chipsets one (AR9280) gets never detected and the other one gets detected most of the time but not always (QCA9882). With Intel modules on the other hand, we can't reproduce the issue. It's the same behaviour as described in the commit above, the link training fails and therefore the link is signalized as down. If a link is successfully established (QCA9882) we don't see any errors during communication.

Do you know if we have the same possibility on the Armada 385 to tune the PCI Express pulse width as you proposed it for the Armada 370?
Unfortunately the PCIe Phy seems to be quite different to the one from the Armada 370.

Best regards
Stefan