[U-Boot] [PATCH v3] rockchip: dts: rk3399: sync with kernel dts

Dr. Philipp Tomsich philipp.tomsich at theobroma-systems.com
Wed Apr 26 10:27:01 UTC 2017


Kever,

I addressed the deprecation of ‘clock-freq-min-max’ in:
	https://patchwork.ozlabs.org/patch/754607/ <https://patchwork.ozlabs.org/patch/754607/>
So you can safely remove this property from the DTS, once my patch for
the driver is merged.

Given that ‘clock-freq-min-max’ is deprecated in Linux, I’d rather not re-add
for our DTS.

Cheers,
Philipp.

p.s.: You’ll may also need another patch (https://patchwork.ozlabs.org/patch/754608/ <https://patchwork.ozlabs.org/patch/754608/>)
to ensure that the renamed clock-entries for sdmmc work with the clk-driver.

> On 26 Apr 2017, at 12:19, Kever Yang <kever.yang at rock-chips.com> wrote:
> 
> The kernel dts has update a lot since the first time we commit rk3399.dtsi,
> sync with kernel for further development.
> 
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
> 
> Changes in v3:
> - add clock-freq-min-max for dwmmc which is a must in rockchip-dw driver
> 
> arch/arm/dts/rk3399.dtsi                 | 1286 +++++++++++++++++++++++++-----
> include/dt-bindings/pinctrl/rockchip.h   |   35 +-
> include/dt-bindings/power/rk3399-power.h |   53 ++
> 3 files changed, 1172 insertions(+), 202 deletions(-)
> create mode 100644 include/dt-bindings/power/rk3399-power.h
> 
> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
> index d94d780..e3792b7 100644
> --- a/arch/arm/dts/rk3399.dtsi
> +++ b/arch/arm/dts/rk3399.dtsi
> @@ -1,5 +1,5 @@
> /*
> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
>  *
>  * SPDX-License-Identifier:	GPL-2.0+
>  */
> @@ -9,6 +9,8 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3399-power.h>
> +#include <dt-bindings/thermal/thermal.h>
> #define USB_CLASS_HUB			9
> 
> / {
> @@ -19,6 +21,15 @@
> 	#size-cells = <2>;
> 
> 	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		i2c2 = &i2c2;
> +		i2c3 = &i2c3;
> +		i2c4 = &i2c4;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		i2c7 = &i2c7;
> +		i2c8 = &i2c8;
> 		serial0 = &uart0;
> 		serial1 = &uart1;
> 		serial2 = &uart2;
> @@ -110,6 +121,16 @@
> 		};
> 	};
> 
> +	pmu_a53 {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> +	};
> +
> +	pmu_a72 {
> +		compatible = "arm,cortex-a72-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
> +	};
> +
> 	psci {
> 		compatible = "arm,psci-1.0";
> 		method = "smc";
> @@ -117,10 +138,11 @@
> 
> 	timer {
> 		compatible = "arm,armv8-timer";
> -		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> -			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> -			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> -			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> +		arm,no-tick-in-suspend;
> 	};
> 
> 	xin24m: xin24m {
> @@ -139,8 +161,8 @@
> 		dmac_bus: dma-controller at ff6d0000 {
> 			compatible = "arm,pl330", "arm,primecell";
> 			reg = <0x0 0xff6d0000 0x0 0x4000>;
> -			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
> 			#dma-cells = <1>;
> 			clocks = <&cru ACLK_DMAC0_PERILP>;
> 			clock-names = "apb_pclk";
> @@ -149,24 +171,93 @@
> 		dmac_peri: dma-controller at ff6e0000 {
> 			compatible = "arm,pl330", "arm,primecell";
> 			reg = <0x0 0xff6e0000 0x0 0x4000>;
> -			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
> 			#dma-cells = <1>;
> 			clocks = <&cru ACLK_DMAC1_PERILP>;
> 			clock-names = "apb_pclk";
> 		};
> 	};
> 
> +	pcie0: pcie at f8000000 {
> +		compatible = "rockchip,rk3399-pcie";
> +		reg = <0x0 0xf8000000 0x0 0x2000000>,
> +		      <0x0 0xfd000000 0x0 0x1000000>;
> +		reg-names = "axi-base", "apb-base";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		#interrupt-cells = <1>;
> +		aspm-no-l0s;
> +		bus-range = <0x0 0x1>;
> +		clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
> +			 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
> +		clock-names = "aclk", "aclk-perf",
> +			      "hclk", "pm";
> +		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "legacy", "client";
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie0_intc 0>,
> +				<0 0 0 2 &pcie0_intc 1>,
> +				<0 0 0 3 &pcie0_intc 2>,
> +				<0 0 0 4 &pcie0_intc 3>;
> +		linux,pci-domain = <0>;
> +		max-link-speed = <1>;
> +		msi-map = <0x0 &its 0x0 0x1000>;
> +		phys = <&pcie_phy>;
> +		phy-names = "pcie-phy";
> +		ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
> +			  0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
> +		resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
> +			 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
> +			 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
> +			 <&cru SRST_A_PCIE>;
> +		reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
> +			      "pm", "pclk", "aclk";
> +		status = "disabled";
> +
> +		pcie0_intc: interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +		};
> +	};
> +
> +	gmac: ethernet at fe300000 {
> +		compatible = "rockchip,rk3399-gmac";
> +		reg = <0x0 0xfe300000 0x0 0x10000>;
> +		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "macirq";
> +		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
> +			 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
> +			 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
> +			 <&cru PCLK_GMAC>;
> +		clock-names = "stmmaceth", "mac_clk_rx",
> +			      "mac_clk_tx", "clk_mac_ref",
> +			      "clk_mac_refout", "aclk_mac",
> +			      "pclk_mac";
> +		power-domains = <&power RK3399_PD_GMAC>;
> +		resets = <&cru SRST_A_GMAC>;
> +		reset-names = "stmmaceth";
> +		rockchip,grf = <&grf>;
> +		status = "disabled";
> +	};
> +
> 	sdio0: dwmmc at fe310000 {
> 		compatible = "rockchip,rk3399-dw-mshc",
> 			     "rockchip,rk3288-dw-mshc";
> 		reg = <0x0 0xfe310000 0x0 0x4000>;
> -		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
> +		max-frequency = <150000000>;
> 		clock-freq-min-max = <400000 150000000>;
> 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
> 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
> 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> 		fifo-depth = <0x100>;
> +		power-domains = <&power RK3399_PD_SDIOAUDIO>;
> +		resets = <&cru SRST_SDIO0>;
> +		reset-names = "reset";
> 		status = "disabled";
> 	};
> 
> @@ -174,14 +265,16 @@
> 		compatible = "rockchip,rk3399-dw-mshc",
> 			     "rockchip,rk3288-dw-mshc";
> 		reg = <0x0 0xfe320000 0x0 0x4000>;
> -		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
> +		max-frequency = <150000000>;
> 		clock-freq-min-max = <400000 150000000>;
> -		clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
> +		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
> 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
> -		clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
> -		pinctrl-names = "default";
> -		pinctrl-0 = <&sdmmc_clk>;
> +		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> 		fifo-depth = <0x100>;
> +		power-domains = <&power RK3399_PD_SD>;
> +		resets = <&cru SRST_SDMMC>;
> +		reset-names = "reset";
> 		status = "disabled";
> 	};
> 
> @@ -189,50 +282,74 @@
> 		u-boot,dm-pre-reloc;
> 		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> 		reg = <0x0 0xfe330000 0x0 0x10000>;
> -		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
> +		arasan,soc-ctl-syscon = <&grf>;
> 		assigned-clocks = <&cru SCLK_EMMC>;
> 		assigned-clock-rates = <200000000>;
> 		max-frequency = <200000000>;
> 		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> 		clock-names = "clk_xin", "clk_ahb";
> +		clock-output-names = "emmc_cardclock";
> +		#clock-cells = <0>;
> 		phys = <&emmc_phy>;
> 		phy-names = "phy_arasan";
> +		power-domains = <&power RK3399_PD_EMMC>;
> 		status = "disabled";
> 	};
> 
> 	usb_host0_ehci: usb at fe380000 {
> 		compatible = "generic-ehci";
> 		reg = <0x0 0xfe380000 0x0 0x20000>;
> -		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
> -		clock-names = "hclk_host0", "hclk_host0_arb";
> +		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
> +			 <&u2phy0>;
> +		clock-names = "usbhost", "arbiter",
> +			      "utmi";
> +		phys = <&u2phy0_host>;
> +		phy-names = "usb";
> +		power-domains = <&power RK3399_PD_PERIHP>;
> 		status = "disabled";
> 	};
> 
> 	usb_host0_ohci: usb at fe3a0000 {
> 		compatible = "generic-ohci";
> 		reg = <0x0 0xfe3a0000 0x0 0x20000>;
> -		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
> -		clock-names = "hclk_host0", "hclk_host0_arb";
> +		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
> +			 <&u2phy0>;
> +		clock-names = "usbhost", "arbiter",
> +			      "utmi";
> +		phys = <&u2phy0_host>;
> +		phy-names = "usb";
> +		power-domains = <&power RK3399_PD_PERIHP>;
> 		status = "disabled";
> 	};
> 
> 	usb_host1_ehci: usb at fe3c0000 {
> 		compatible = "generic-ehci";
> 		reg = <0x0 0xfe3c0000 0x0 0x20000>;
> -		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
> -		clock-names = "hclk_host1", "hclk_host1_arb";
> +		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
> +			 <&u2phy1>;
> +		clock-names = "usbhost", "arbiter",
> +			      "utmi";
> +		phys = <&u2phy1_host>;
> +		phy-names = "usb";
> +		power-domains = <&power RK3399_PD_PERIHP>;
> 		status = "disabled";
> 	};
> 
> 	usb_host1_ohci: usb at fe3e0000 {
> 		compatible = "generic-ohci";
> 		reg = <0x0 0xfe3e0000 0x0 0x20000>;
> -		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
> -		clock-names = "hclk_host1", "hclk_host1_arb";
> +		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
> +			 <&u2phy1>;
> +		clock-names = "usbhost", "arbiter",
> +			      "utmi";
> +		phys = <&u2phy1_host>;
> +		phy-names = "usb";
> +		power-domains = <&power RK3399_PD_PERIHP>;
> 		status = "disabled";
> 	};
> 
> @@ -280,7 +397,7 @@
> 
> 	gic: interrupt-controller at fee00000 {
> 		compatible = "arm,gic-v3";
> -		#interrupt-cells = <3>;
> +		#interrupt-cells = <4>;
> 		#address-cells = <2>;
> 		#size-cells = <2>;
> 		ranges;
> @@ -291,12 +408,124 @@
> 		      <0x0 0xfff00000 0 0x10000>, /* GICC */
> 		      <0x0 0xfff10000 0 0x10000>, /* GICH */
> 		      <0x0 0xfff20000 0 0x10000>; /* GICV */
> -		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> 		its: interrupt-controller at fee20000 {
> 			compatible = "arm,gic-v3-its";
> 			msi-controller;
> 			reg = <0x0 0xfee20000 0x0 0x20000>;
> 		};
> +
> +		ppi-partitions {
> +			ppi_cluster0: interrupt-partition-0 {
> +				affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
> +			};
> +
> +			ppi_cluster1: interrupt-partition-1 {
> +				affinity = <&cpu_b0 &cpu_b1>;
> +			};
> +		};
> +	};
> +
> +	saradc: saradc at ff100000 {
> +		compatible = "rockchip,rk3399-saradc";
> +		reg = <0x0 0xff100000 0x0 0x100>;
> +		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
> +		#io-channel-cells = <1>;
> +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
> +		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_P_SARADC>;
> +		reset-names = "saradc-apb";
> +		status = "disabled";
> +	};
> +
> +	i2c1: i2c at ff110000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff110000 0x0 0x1000>;
> +		assigned-clocks = <&cru SCLK_I2C1>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c1_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c2: i2c at ff120000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff120000 0x0 0x1000>;
> +		assigned-clocks = <&cru SCLK_I2C2>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c2_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c3: i2c at ff130000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff130000 0x0 0x1000>;
> +		assigned-clocks = <&cru SCLK_I2C3>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c3_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c5: i2c at ff140000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff140000 0x0 0x1000>;
> +		assigned-clocks = <&cru SCLK_I2C5>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c5_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c6: i2c at ff150000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff150000 0x0 0x1000>;
> +		assigned-clocks = <&cru SCLK_I2C6>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c6_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c7: i2c at ff160000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff160000 0x0 0x1000>;
> +		assigned-clocks = <&cru SCLK_I2C7>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c7_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> 	};
> 
> 	uart0: serial at ff180000 {
> @@ -304,7 +533,7 @@
> 		reg = <0x0 0xff180000 0x0 0x100>;
> 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> 		clock-names = "baudclk", "apb_pclk";
> -		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> 		reg-shift = <2>;
> 		reg-io-width = <4>;
> 		pinctrl-names = "default";
> @@ -317,7 +546,7 @@
> 		reg = <0x0 0xff190000 0x0 0x100>;
> 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> 		clock-names = "baudclk", "apb_pclk";
> -		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
> 		reg-shift = <2>;
> 		reg-io-width = <4>;
> 		pinctrl-names = "default";
> @@ -330,7 +559,7 @@
> 		reg = <0x0 0xff1a0000 0x0 0x100>;
> 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> 		clock-names = "baudclk", "apb_pclk";
> -		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
> 		clock-frequency = <24000000>;
> 		reg-shift = <2>;
> 		reg-io-width = <4>;
> @@ -344,7 +573,7 @@
> 		reg = <0x0 0xff1b0000 0x0 0x100>;
> 		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> 		clock-names = "baudclk", "apb_pclk";
> -		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
> 		reg-shift = <2>;
> 		reg-io-width = <4>;
> 		pinctrl-names = "default";
> @@ -357,7 +586,7 @@
> 		reg = <0x0 0xff1c0000 0x0 0x1000>;
> 		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
> 		clock-names = "spiclk", "apb_pclk";
> -		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
> 		#address-cells = <1>;
> @@ -370,7 +599,7 @@
> 		reg = <0x0 0xff1d0000 0x0 0x1000>;
> 		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
> 		clock-names = "spiclk", "apb_pclk";
> -		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
> 		#address-cells = <1>;
> @@ -383,7 +612,7 @@
> 		reg = <0x0 0xff1e0000 0x0 0x1000>;
> 		clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
> 		clock-names = "spiclk", "apb_pclk";
> -		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
> 		#address-cells = <1>;
> @@ -396,7 +625,7 @@
> 		reg = <0x0 0xff1f0000 0x0 0x1000>;
> 		clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
> 		clock-names = "spiclk", "apb_pclk";
> -		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
> 		#address-cells = <1>;
> @@ -409,7 +638,7 @@
> 		reg = <0x0 0xff200000 0x0 0x1000>;
> 		clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
> 		clock-names = "spiclk", "apb_pclk";
> -		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
> 		#address-cells = <1>;
> @@ -417,6 +646,375 @@
> 		status = "disabled";
> 	};
> 
> +	thermal_zones: thermal-zones {
> +		cpu_thermal: cpu {
> +			polling-delay-passive = <100>;
> +			polling-delay = <1000>;
> +
> +			thermal-sensors = <&tsadc 0>;
> +
> +			trips {
> +				cpu_alert0: cpu_alert0 {
> +					temperature = <70000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +				cpu_alert1: cpu_alert1 {
> +					temperature = <75000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +				cpu_crit: cpu_crit {
> +					temperature = <95000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_alert0>;
> +					cooling-device =
> +						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu_alert1>;
> +					cooling-device =
> +						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
> +		};
> +
> +		gpu_thermal: gpu {
> +			polling-delay-passive = <100>;
> +			polling-delay = <1000>;
> +
> +			thermal-sensors = <&tsadc 1>;
> +
> +			trips {
> +				gpu_alert0: gpu_alert0 {
> +					temperature = <75000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +				gpu_crit: gpu_crit {
> +					temperature = <95000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&gpu_alert0>;
> +					cooling-device =
> +						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
> +		};
> +	};
> +
> +	tsadc: tsadc at ff260000 {
> +		compatible = "rockchip,rk3399-tsadc";
> +		reg = <0x0 0xff260000 0x0 0x100>;
> +		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +		assigned-clocks = <&cru SCLK_TSADC>;
> +		assigned-clock-rates = <750000>;
> +		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
> +		clock-names = "tsadc", "apb_pclk";
> +		resets = <&cru SRST_TSADC>;
> +		reset-names = "tsadc-apb";
> +		rockchip,grf = <&grf>;
> +		rockchip,hw-tshut-temp = <95000>;
> +		pinctrl-names = "init", "default", "sleep";
> +		pinctrl-0 = <&otp_gpio>;
> +		pinctrl-1 = <&otp_out>;
> +		pinctrl-2 = <&otp_gpio>;
> +		#thermal-sensor-cells = <1>;
> +		status = "disabled";
> +	};
> +
> +	qos_emmc: qos at ffa58000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa58000 0x0 0x20>;
> +	};
> +
> +	qos_gmac: qos at ffa5c000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa5c000 0x0 0x20>;
> +	};
> +
> +	qos_pcie: qos at ffa60080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa60080 0x0 0x20>;
> +	};
> +
> +	qos_usb_host0: qos at ffa60100 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa60100 0x0 0x20>;
> +	};
> +
> +	qos_usb_host1: qos at ffa60180 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa60180 0x0 0x20>;
> +	};
> +
> +	qos_usb_otg0: qos at ffa70000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa70000 0x0 0x20>;
> +	};
> +
> +	qos_usb_otg1: qos at ffa70080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa70080 0x0 0x20>;
> +	};
> +
> +	qos_sd: qos at ffa74000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa74000 0x0 0x20>;
> +	};
> +
> +	qos_sdioaudio: qos at ffa76000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa76000 0x0 0x20>;
> +	};
> +
> +	qos_hdcp: qos at ffa90000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa90000 0x0 0x20>;
> +	};
> +
> +	qos_iep: qos at ffa98000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa98000 0x0 0x20>;
> +	};
> +
> +	qos_isp0_m0: qos at ffaa0000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffaa0000 0x0 0x20>;
> +	};
> +
> +	qos_isp0_m1: qos at ffaa0080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffaa0080 0x0 0x20>;
> +	};
> +
> +	qos_isp1_m0: qos at ffaa8000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffaa8000 0x0 0x20>;
> +	};
> +
> +	qos_isp1_m1: qos at ffaa8080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffaa8080 0x0 0x20>;
> +	};
> +
> +	qos_rga_r: qos at ffab0000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffab0000 0x0 0x20>;
> +	};
> +
> +	qos_rga_w: qos at ffab0080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffab0080 0x0 0x20>;
> +	};
> +
> +	qos_video_m0: qos at ffab8000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffab8000 0x0 0x20>;
> +	};
> +
> +	qos_video_m1_r: qos at ffac0000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffac0000 0x0 0x20>;
> +	};
> +
> +	qos_video_m1_w: qos at ffac0080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffac0080 0x0 0x20>;
> +	};
> +
> +	qos_vop_big_r: qos at ffac8000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffac8000 0x0 0x20>;
> +	};
> +
> +	qos_vop_big_w: qos at ffac8080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffac8080 0x0 0x20>;
> +	};
> +
> +	qos_vop_little: qos at ffad0000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffad0000 0x0 0x20>;
> +	};
> +
> +	qos_perihp: qos at ffad8080 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffad8080 0x0 0x20>;
> +	};
> +
> +	qos_gpu: qos at ffae0000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffae0000 0x0 0x20>;
> +	};
> +
> +	pmu: power-management at ff310000 {
> +		compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
> +		reg = <0x0 0xff310000 0x0 0x1000>;
> +
> +		/*
> +		 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
> +		 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
> +		 * Some of the power domains are grouped together for every
> +		 * voltage domain.
> +		 * The detail contents as below.
> +		 */
> +		power: power-controller {
> +			compatible = "rockchip,rk3399-power-controller";
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* These power domains are grouped by VD_CENTER */
> +			pd_iep at RK3399_PD_IEP {
> +				reg = <RK3399_PD_IEP>;
> +				clocks = <&cru ACLK_IEP>,
> +					 <&cru HCLK_IEP>;
> +				pm_qos = <&qos_iep>;
> +			};
> +			pd_rga at RK3399_PD_RGA {
> +				reg = <RK3399_PD_RGA>;
> +				clocks = <&cru ACLK_RGA>,
> +					 <&cru HCLK_RGA>;
> +				pm_qos = <&qos_rga_r>,
> +					 <&qos_rga_w>;
> +			};
> +			pd_vcodec at RK3399_PD_VCODEC {
> +				reg = <RK3399_PD_VCODEC>;
> +				clocks = <&cru ACLK_VCODEC>,
> +					 <&cru HCLK_VCODEC>;
> +				pm_qos = <&qos_video_m0>;
> +			};
> +			pd_vdu at RK3399_PD_VDU {
> +				reg = <RK3399_PD_VDU>;
> +				clocks = <&cru ACLK_VDU>,
> +					 <&cru HCLK_VDU>;
> +				pm_qos = <&qos_video_m1_r>,
> +					 <&qos_video_m1_w>;
> +			};
> +
> +			/* These power domains are grouped by VD_GPU */
> +			pd_gpu at RK3399_PD_GPU {
> +				reg = <RK3399_PD_GPU>;
> +				clocks = <&cru ACLK_GPU>;
> +				pm_qos = <&qos_gpu>;
> +			};
> +
> +			/* These power domains are grouped by VD_LOGIC */
> +			pd_edp at RK3399_PD_EDP {
> +				reg = <RK3399_PD_EDP>;
> +				clocks = <&cru PCLK_EDP_CTRL>;
> +			};
> +			pd_emmc at RK3399_PD_EMMC {
> +				reg = <RK3399_PD_EMMC>;
> +				clocks = <&cru ACLK_EMMC>;
> +				pm_qos = <&qos_emmc>;
> +			};
> +			pd_gmac at RK3399_PD_GMAC {
> +				reg = <RK3399_PD_GMAC>;
> +				clocks = <&cru ACLK_GMAC>,
> +					 <&cru PCLK_GMAC>;
> +				pm_qos = <&qos_gmac>;
> +			};
> +			pd_perihp at RK3399_PD_PERIHP {
> +				reg = <RK3399_PD_PERIHP>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				clocks = <&cru ACLK_PERIHP>;
> +				pm_qos = <&qos_perihp>,
> +					 <&qos_pcie>,
> +					 <&qos_usb_host0>,
> +					 <&qos_usb_host1>;
> +
> +				pd_sd at RK3399_PD_SD {
> +					reg = <RK3399_PD_SD>;
> +					clocks = <&cru HCLK_SDMMC>,
> +						 <&cru SCLK_SDMMC>;
> +					pm_qos = <&qos_sd>;
> +				};
> +			};
> +			pd_sdioaudio at RK3399_PD_SDIOAUDIO {
> +				reg = <RK3399_PD_SDIOAUDIO>;
> +				clocks = <&cru HCLK_SDIO>;
> +				pm_qos = <&qos_sdioaudio>;
> +			};
> +			pd_usb3 at RK3399_PD_USB3 {
> +				reg = <RK3399_PD_USB3>;
> +				clocks = <&cru ACLK_USB3>;
> +				pm_qos = <&qos_usb_otg0>,
> +					 <&qos_usb_otg1>;
> +			};
> +			pd_vio at RK3399_PD_VIO {
> +				reg = <RK3399_PD_VIO>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				pd_hdcp at RK3399_PD_HDCP {
> +					reg = <RK3399_PD_HDCP>;
> +					clocks = <&cru ACLK_HDCP>,
> +						 <&cru HCLK_HDCP>,
> +						 <&cru PCLK_HDCP>;
> +					pm_qos = <&qos_hdcp>;
> +				};
> +				pd_isp0 at RK3399_PD_ISP0 {
> +					reg = <RK3399_PD_ISP0>;
> +					clocks = <&cru ACLK_ISP0>,
> +						 <&cru HCLK_ISP0>;
> +					pm_qos = <&qos_isp0_m0>,
> +						 <&qos_isp0_m1>;
> +				};
> +				pd_isp1 at RK3399_PD_ISP1 {
> +					reg = <RK3399_PD_ISP1>;
> +					clocks = <&cru ACLK_ISP1>,
> +						 <&cru HCLK_ISP1>;
> +					pm_qos = <&qos_isp1_m0>,
> +						 <&qos_isp1_m1>;
> +				};
> +				pd_tcpc0 at RK3399_PD_TCPC0 {
> +					reg = <RK3399_PD_TCPD0>;
> +					clocks = <&cru SCLK_UPHY0_TCPDCORE>,
> +						 <&cru SCLK_UPHY0_TCPDPHY_REF>;
> +				};
> +				pd_tcpc1 at RK3399_PD_TCPC1 {
> +					reg = <RK3399_PD_TCPD1>;
> +					clocks = <&cru SCLK_UPHY1_TCPDCORE>,
> +						 <&cru SCLK_UPHY1_TCPDPHY_REF>;
> +				};
> +				pd_vo at RK3399_PD_VO {
> +					reg = <RK3399_PD_VO>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					pd_vopb at RK3399_PD_VOPB {
> +						reg = <RK3399_PD_VOPB>;
> +						clocks = <&cru ACLK_VOP0>,
> +							 <&cru HCLK_VOP0>;
> +						pm_qos = <&qos_vop_big_r>,
> +							 <&qos_vop_big_w>;
> +					};
> +					pd_vopl at RK3399_PD_VOPL {
> +						reg = <RK3399_PD_VOPL>;
> +						clocks = <&cru ACLK_VOP1>,
> +							 <&cru HCLK_VOP1>;
> +						pm_qos = <&qos_vop_little>;
> +					};
> +				};
> +			};
> +		};
> +	};
> +
> 	pmugrf: syscon at ff320000 {
> 		u-boot,dm-pre-reloc;
> 		compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
> @@ -441,7 +1039,7 @@
> 		reg = <0x0 0xff350000 0x0 0x1000>;
> 		clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
> 		clock-names = "spiclk", "apb_pclk";
> -		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
> 		#address-cells = <1>;
> @@ -454,7 +1052,7 @@
> 		reg = <0x0 0xff370000 0x0 0x100>;
> 		clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
> 		clock-names = "baudclk", "apb_pclk";
> -		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
> 		reg-shift = <2>;
> 		reg-io-width = <4>;
> 		pinctrl-names = "default";
> @@ -462,6 +1060,51 @@
> 		status = "disabled";
> 	};
> 
> +	i2c0: i2c at ff3c0000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff3c0000 0x0 0x1000>;
> +		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c0_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c4: i2c at ff3d0000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff3d0000 0x0 0x1000>;
> +		assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c4_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c8: i2c at ff3e0000 {
> +		compatible = "rockchip,rk3399-i2c";
> +		reg = <0x0 0xff3e0000 0x0 0x1000>;
> +		assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
> +		assigned-clock-rates = <200000000>;
> +		clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
> +		clock-names = "i2c", "pclk";
> +		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&i2c8_xfer>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> 	pwm0: pwm at ff420000 {
> 		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
> 		reg = <0x0 0xff420000 0x0 0x10>;
> @@ -538,10 +1181,43 @@
> 		       0x0 0xffa8c000 0x0 0x1000>;
> 	};
> 
> +	efuse0: efuse at ff690000 {
> +		compatible = "rockchip,rk3399-efuse";
> +		reg = <0x0 0xff690000 0x0 0x80>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		clocks = <&cru PCLK_EFUSE1024NS>;
> +		clock-names = "pclk_efuse";
> +
> +		/* Data cells */
> +		cpu_id: cpu-id at 7 {
> +			reg = <0x07 0x10>;
> +		};
> +		cpub_leakage: cpu-leakage at 17 {
> +			reg = <0x17 0x1>;
> +		};
> +		gpu_leakage: gpu-leakage at 18 {
> +			reg = <0x18 0x1>;
> +		};
> +		center_leakage: center-leakage at 19 {
> +			reg = <0x19 0x1>;
> +		};
> +		cpul_leakage: cpu-leakage at 1a {
> +			reg = <0x1a 0x1>;
> +		};
> +		logic_leakage: logic-leakage at 1b {
> +			reg = <0x1b 0x1>;
> +		};
> +		wafer_info: wafer-info at 1c {
> +			reg = <0x1c 0x1>;
> +		};
> +	};
> +
> 	pmucru: pmu-clock-controller at ff750000 {
> 		u-boot,dm-pre-reloc;
> 		compatible = "rockchip,rk3399-pmucru";
> 		reg = <0x0 0xff750000 0x0 0x1000>;
> +		rockchip,grf = <&pmugrf>;
> 		#clock-cells = <1>;
> 		#reset-cells = <1>;
> 		assigned-clocks = <&pmucru PLL_PPLL>;
> @@ -552,6 +1228,7 @@
> 		u-boot,dm-pre-reloc;
> 		compatible = "rockchip,rk3399-cru";
> 		reg = <0x0 0xff760000 0x0 0x1000>;
> +		rockchip,grf = <&grf>;
> 		#clock-cells = <1>;
> 		#reset-cells = <1>;
> 		assigned-clocks =
> @@ -560,7 +1237,7 @@
> 			<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
> 			<&cru PCLK_PERIHP>,
> 			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
> -			<&cru PCLK_PERILP0>,
> +			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
> 			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
> 		assigned-clock-rates =
> 			 <594000000>,  <800000000>,
> @@ -568,7 +1245,7 @@
> 			 <150000000>,   <75000000>,
> 			  <37500000>,
> 			 <100000000>,  <100000000>,
> -			  <50000000>,
> +			  <50000000>, <600000000>,
> 			 <100000000>,   <50000000>;
> 	};
> 
> @@ -584,50 +1261,106 @@
> 			status = "disabled";
> 		};
> 
> +		u2phy0: usb2-phy at e450 {
> +			compatible = "rockchip,rk3399-usb2phy";
> +			reg = <0xe450 0x10>;
> +			clocks = <&cru SCLK_USB2PHY0_REF>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			clock-output-names = "clk_usbphy0_480m";
> +			status = "disabled";
> +
> +			u2phy0_host: host-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> +				interrupt-names = "linestate";
> +				status = "disabled";
> +			};
> +
> +			u2phy0_otg: otg-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> +					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> +					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> +				interrupt-names = "otg-bvalid", "otg-id",
> +						  "linestate";
> +				status = "disabled";
> +			};
> +		};
> +
> +		u2phy1: usb2-phy at e460 {
> +			compatible = "rockchip,rk3399-usb2phy";
> +			reg = <0xe460 0x10>;
> +			clocks = <&cru SCLK_USB2PHY1_REF>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			clock-output-names = "clk_usbphy1_480m";
> +			status = "disabled";
> +
> +			u2phy1_host: host-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> +				interrupt-names = "linestate";
> +				status = "disabled";
> +			};
> +
> +			u2phy1_otg: otg-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> +					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> +					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> +				interrupt-names = "otg-bvalid", "otg-id",
> +						  "linestate";
> +				status = "disabled";
> +			};
> +		};
> +
> 		emmc_phy: phy at f780 {
> 			compatible = "rockchip,rk3399-emmc-phy";
> 			reg = <0xf780 0x24>;
> +			clocks = <&sdhci>;
> +			clock-names = "emmcclk";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		pcie_phy: pcie-phy {
> +			compatible = "rockchip,rk3399-pcie-phy";
> +			clocks = <&cru SCLK_PCIEPHY_REF>;
> +			clock-names = "refclk";
> 			#phy-cells = <0>;
> +			resets = <&cru SRST_PCIEPHY>;
> +			reset-names = "phy";
> 			status = "disabled";
> 		};
> 	};
> 
> -	watchdog at ff840000 {
> +	watchdog at ff848000 {
> 		compatible = "snps,dw-wdt";
> -		reg = <0x0 0xff840000 0x0 0x100>;
> +		reg = <0x0 0xff848000 0x0 0x100>;
> 		clocks = <&cru PCLK_WDT>;
> -		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> -	};
> -
> -        gmac: eth at fe300000 {
> -                compatible = "rockchip,rk3399-gmac";
> -                reg = <0x0 0xfe300000 0x0 0x10000>;
> -                rockchip,grf = <&grf>;
> -                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
> -                interrupt-names = "macirq";
> -                clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
> -                         <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
> -                         <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
> -                         <&cru PCLK_GMAC>;
> -                clock-names = "stmmaceth", "mac_clk_rx",
> -                              "mac_clk_tx", "clk_mac_ref",
> -                              "clk_mac_refout", "aclk_mac",
> -                              "pclk_mac";
> -                resets = <&cru SRST_A_GMAC>;
> -                reset-names = "stmmaceth";
> -                status = "disabled";
> -        };
> +		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
> +	};
> +
> +	rktimer: rktimer at ff850000 {
> +		compatible = "rockchip,rk3399-timer";
> +		reg = <0x0 0xff850000 0x0 0x1000>;
> +		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
> +		clock-names = "pclk", "timer";
> +	};
> 
> 	spdif: spdif at ff870000 {
> 		compatible = "rockchip,rk3399-spdif";
> 		reg = <0x0 0xff870000 0x0 0x1000>;
> -		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
> 		dmas = <&dmac_bus 7>;
> 		dma-names = "tx";
> 		clock-names = "mclk", "hclk";
> 		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&spdif_bus>;
> +		power-domains = <&power RK3399_PD_SDIOAUDIO>;
> 		status = "disabled";
> 	};
> 
> @@ -635,37 +1368,40 @@
> 		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
> 		reg = <0x0 0xff880000 0x0 0x1000>;
> 		rockchip,grf = <&grf>;
> -		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
> 		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
> 		dma-names = "tx", "rx";
> 		clock-names = "i2s_clk", "i2s_hclk";
> 		clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&i2s0_8ch_bus>;
> +		power-domains = <&power RK3399_PD_SDIOAUDIO>;
> 		status = "disabled";
> 	};
> 
> 	i2s1: i2s at ff890000 {
> 		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
> 		reg = <0x0 0xff890000 0x0 0x1000>;
> -		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
> 		dmas = <&dmac_bus 2>, <&dmac_bus 3>;
> 		dma-names = "tx", "rx";
> 		clock-names = "i2s_clk", "i2s_hclk";
> 		clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
> 		pinctrl-names = "default";
> 		pinctrl-0 = <&i2s1_2ch_bus>;
> +		power-domains = <&power RK3399_PD_SDIOAUDIO>;
> 		status = "disabled";
> 	};
> 
> 	i2s2: i2s at ff8a0000 {
> 		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
> 		reg = <0x0 0xff8a0000 0x0 0x1000>;
> -		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
> 		dmas = <&dmac_bus 4>, <&dmac_bus 5>;
> 		dma-names = "tx", "rx";
> 		clock-names = "i2s_clk", "i2s_hclk";
> 		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
> +		power-domains = <&power RK3399_PD_SDIOAUDIO>;
> 		status = "disabled";
> 	};
> 
> @@ -697,7 +1433,7 @@
> 			compatible = "rockchip,gpio-bank";
> 			reg = <0x0 0xff720000 0x0 0x100>;
> 			clocks = <&pmucru PCLK_GPIO0_PMU>;
> -			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
> 
> 			gpio-controller;
> 			#gpio-cells = <0x2>;
> @@ -710,7 +1446,7 @@
> 			compatible = "rockchip,gpio-bank";
> 			reg = <0x0 0xff730000 0x0 0x100>;
> 			clocks = <&pmucru PCLK_GPIO1_PMU>;
> -			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
> 
> 			gpio-controller;
> 			#gpio-cells = <0x2>;
> @@ -723,7 +1459,7 @@
> 			compatible = "rockchip,gpio-bank";
> 			reg = <0x0 0xff780000 0x0 0x100>;
> 			clocks = <&cru PCLK_GPIO2>;
> -			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
> 
> 			gpio-controller;
> 			#gpio-cells = <0x2>;
> @@ -736,7 +1472,7 @@
> 			compatible = "rockchip,gpio-bank";
> 			reg = <0x0 0xff788000 0x0 0x100>;
> 			clocks = <&cru PCLK_GPIO3>;
> -			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
> 
> 			gpio-controller;
> 			#gpio-cells = <0x2>;
> @@ -749,7 +1485,7 @@
> 			compatible = "rockchip,gpio-bank";
> 			reg = <0x0 0xff790000 0x0 0x100>;
> 			clocks = <&cru PCLK_GPIO4>;
> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
> 
> 			gpio-controller;
> 			#gpio-cells = <0x2>;
> @@ -800,427 +1536,575 @@
> 			drive-strength = <13>;
> 		};
> 
> +		clock {
> +			clk_32k: clk-32k {
> +				rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>;
> +			};
> +		};
> +
> +		edp {
> +			edp_hpd: edp-hpd {
> +				rockchip,pins =
> +					<4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
> +			};
> +		};
> +
> +		gmac {
> +			rgmii_pins: rgmii-pins {
> +				rockchip,pins =
> +					/* mac_txclk */
> +					<3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_rxclk */
> +					<3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_mdio */
> +					<3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_txen */
> +					<3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_clk */
> +					<3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxdv */
> +					<3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_mdc */
> +					<3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxd1 */
> +					<3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxd0 */
> +					<3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_txd1 */
> +					<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_txd0 */
> +					<3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_rxd3 */
> +					<3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxd2 */
> +					<3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_txd3 */
> +					<3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_txd2 */
> +					<3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>;
> +			};
> +
> +			rmii_pins: rmii-pins {
> +				rockchip,pins =
> +					/* mac_mdio */
> +					<3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_txen */
> +					<3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_clk */
> +					<3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxer */
> +					<3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxdv */
> +					<3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_mdc */
> +					<3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxd1 */
> +					<3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_rxd0 */
> +					<3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
> +					/* mac_txd1 */
> +					<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>,
> +					/* mac_txd0 */
> +					<3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>;
> +			};
> +		};
> +
> 		i2c0 {
> 			i2c0_xfer: i2c0-xfer {
> 				rockchip,pins =
> -					<1 15 RK_FUNC_2 &pcfg_pull_none>,
> -					<1 16 RK_FUNC_2 &pcfg_pull_none>;
> +					<1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
> +					<1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c1 {
> 			i2c1_xfer: i2c1-xfer {
> 				rockchip,pins =
> -					<4 2 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 1 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c2 {
> 			i2c2_xfer: i2c2-xfer {
> 				rockchip,pins =
> -					<2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
> -					<2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
> +					<2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>,
> +					<2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>;
> 			};
> 		};
> 
> 		i2c3 {
> 			i2c3_xfer: i2c3-xfer {
> 				rockchip,pins =
> -					<4 17 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 16 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c4 {
> 			i2c4_xfer: i2c4-xfer {
> 				rockchip,pins =
> -					<1 12 RK_FUNC_1 &pcfg_pull_none>,
> -					<1 11 RK_FUNC_1 &pcfg_pull_none>;
> +					<1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
> +					<1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c5 {
> 			i2c5_xfer: i2c5-xfer {
> 				rockchip,pins =
> -					<3 11 RK_FUNC_2 &pcfg_pull_none>,
> -					<3 10 RK_FUNC_2 &pcfg_pull_none>;
> +					<3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
> +					<3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c6 {
> 			i2c6_xfer: i2c6-xfer {
> 				rockchip,pins =
> -					<2 10 RK_FUNC_2 &pcfg_pull_none>,
> -					<2 9 RK_FUNC_2 &pcfg_pull_none>;
> +					<2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
> +					<2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c7 {
> 			i2c7_xfer: i2c7-xfer {
> 				rockchip,pins =
> -					<2 8 RK_FUNC_2 &pcfg_pull_none>,
> -					<2 7 RK_FUNC_2 &pcfg_pull_none>;
> +					<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
> +					<2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2c8 {
> 			i2c8_xfer: i2c8-xfer {
> 				rockchip,pins =
> -					<1 21 RK_FUNC_1 &pcfg_pull_none>,
> -					<1 20 RK_FUNC_1 &pcfg_pull_none>;
> +					<1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
> +					<1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2s0 {
> 			i2s0_8ch_bus: i2s0-8ch-bus {
> 				rockchip,pins =
> -					<3 24 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 25 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 26 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 27 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 28 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 29 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 30 RK_FUNC_1 &pcfg_pull_none>,
> -					<3 31 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 0 RK_FUNC_1 &pcfg_pull_none>;
> +					<3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>,
> +					<3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		i2s1 {
> 			i2s1_2ch_bus: i2s1-2ch-bus {
> 				rockchip,pins =
> -					<4 3 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 4 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 5 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 6 RK_FUNC_1 &pcfg_pull_none>,
> -					<4 7 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
> +					<4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> -		gmac {
> -			rgmii_pins: rgmii-pins {
> +		sdio0 {
> +			sdio0_bus1: sdio0-bus1 {
> 				rockchip,pins =
> -					/* mac_txclk */
> -					<3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
> -					/* mac_rxclk */
> -					<3 14 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_mdio */
> -					<3 13 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_txen */
> -					<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
> -					/* mac_clk */
> -					<3 11 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_rxdv */
> -					<3 9 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_mdc */
> -					<3 8 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_rxd1 */
> -					<3 7 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_rxd0 */
> -					<3 6 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_txd1 */
> -					<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
> -					/* mac_txd0 */
> -					<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
> -					/* mac_rxd3 */
> -					<3 3 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_rxd2 */
> -					<3 2 RK_FUNC_1 &pcfg_pull_none>,
> -					/* mac_txd3 */
> -					<3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
> -					/* mac_txd2 */
> -					<3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
> +					<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_bus4: sdio0-bus4 {
> +				rockchip,pins =
> +					<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
> +					<2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
> +					<2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
> +					<2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_cmd: sdio0-cmd {
> +				rockchip,pins =
> +					<2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_clk: sdio0-clk {
> +				rockchip,pins =
> +					<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
> +			};
> +
> +			sdio0_cd: sdio0-cd {
> +				rockchip,pins =
> +					<2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_pwr: sdio0-pwr {
> +				rockchip,pins =
> +					<2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_bkpwr: sdio0-bkpwr {
> +				rockchip,pins =
> +					<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_wp: sdio0-wp {
> +				rockchip,pins =
> +					<0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +
> +			sdio0_int: sdio0-int {
> +				rockchip,pins =
> +					<0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 		};
> 
> 		sdmmc {
> 			sdmmc_bus1: sdmmc-bus1 {
> 				rockchip,pins =
> -					<4 8 RK_FUNC_1 &pcfg_pull_up>;
> +					<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 
> 			sdmmc_bus4: sdmmc-bus4 {
> 				rockchip,pins =
> -					<4 8 RK_FUNC_1 &pcfg_pull_up>,
> -					<4 9 RK_FUNC_1 &pcfg_pull_up>,
> -					<4 10 RK_FUNC_1 &pcfg_pull_up>,
> -					<4 11 RK_FUNC_1 &pcfg_pull_up>;
> +					<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
> +					<4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
> +					<4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
> +					<4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 
> 			sdmmc_clk: sdmmc-clk {
> 				rockchip,pins =
> -					<4 12 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 
> 			sdmmc_cmd: sdmmc-cmd {
> 				rockchip,pins =
> -					<4 13 RK_FUNC_1 &pcfg_pull_up>;
> +					<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 
> 			sdmmc_cd: sdmcc-cd {
> 				rockchip,pins =
> -					<0 7 RK_FUNC_1 &pcfg_pull_up>;
> +					<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 
> 			sdmmc_wp: sdmmc-wp {
> 				rockchip,pins =
> -					<0 8 RK_FUNC_1 &pcfg_pull_up>;
> +					<0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
> +			};
> +		};
> +
> +		sleep {
> +			ap_pwroff: ap-pwroff {
> +				rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
> +			};
> +
> +			ddrio_pwroff: ddrio-pwroff {
> +				rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		spdif {
> 			spdif_bus: spdif-bus {
> 				rockchip,pins =
> -					<4 21 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
> +			};
> +
> +			spdif_bus_1: spdif-bus-1 {
> +				rockchip,pins =
> +					<3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		spi0 {
> 			spi0_clk: spi0-clk {
> 				rockchip,pins =
> -					<3 6 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi0_cs0: spi0-cs0 {
> 				rockchip,pins =
> -					<3 7 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi0_cs1: spi0-cs1 {
> 				rockchip,pins =
> -					<3 8 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi0_tx: spi0-tx {
> 				rockchip,pins =
> -					<3 5 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi0_rx: spi0-rx {
> 				rockchip,pins =
> -					<3 4 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 		};
> 
> 		spi1 {
> 			spi1_clk: spi1-clk {
> 				rockchip,pins =
> -					<1 9 RK_FUNC_2 &pcfg_pull_up>;
> +					<1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi1_cs0: spi1-cs0 {
> 				rockchip,pins =
> -					<1 10 RK_FUNC_2 &pcfg_pull_up>;
> +					<1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi1_rx: spi1-rx {
> 				rockchip,pins =
> -					<1 7 RK_FUNC_2 &pcfg_pull_up>;
> +					<1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi1_tx: spi1-tx {
> 				rockchip,pins =
> -					<1 8 RK_FUNC_2 &pcfg_pull_up>;
> +					<1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 		};
> 
> 		spi2 {
> 			spi2_clk: spi2-clk {
> 				rockchip,pins =
> -					<2 11 RK_FUNC_1 &pcfg_pull_up>;
> +					<2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 			spi2_cs0: spi2-cs0 {
> 				rockchip,pins =
> -					<2 12 RK_FUNC_1 &pcfg_pull_up>;
> +					<2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 			spi2_rx: spi2-rx {
> 				rockchip,pins =
> -					<2 9 RK_FUNC_1 &pcfg_pull_up>;
> +					<2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 			spi2_tx: spi2-tx {
> 				rockchip,pins =
> -					<2 10 RK_FUNC_1 &pcfg_pull_up>;
> +					<2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 		};
> 
> 		spi3 {
> 			spi3_clk: spi3-clk {
> 				rockchip,pins =
> -					<1 17 RK_FUNC_1 &pcfg_pull_up>;
> +					<1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 			spi3_cs0: spi3-cs0 {
> 				rockchip,pins =
> -					<1 18 RK_FUNC_1 &pcfg_pull_up>;
> +					<1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 			spi3_rx: spi3-rx {
> 				rockchip,pins =
> -					<1 15 RK_FUNC_1 &pcfg_pull_up>;
> +					<1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 			spi3_tx: spi3-tx {
> 				rockchip,pins =
> -					<1 16 RK_FUNC_1 &pcfg_pull_up>;
> +					<1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>;
> 			};
> 		};
> 
> 		spi4 {
> 			spi4_clk: spi4-clk {
> 				rockchip,pins =
> -					<3 2 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi4_cs0: spi4-cs0 {
> 				rockchip,pins =
> -					<3 3 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi4_rx: spi4-rx {
> 				rockchip,pins =
> -					<3 0 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi4_tx: spi4-tx {
> 				rockchip,pins =
> -					<3 1 RK_FUNC_2 &pcfg_pull_up>;
> +					<3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 		};
> 
> 		spi5 {
> 			spi5_clk: spi5-clk {
> 				rockchip,pins =
> -					<2 22 RK_FUNC_2 &pcfg_pull_up>;
> +					<2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi5_cs0: spi5-cs0 {
> 				rockchip,pins =
> -					<2 23 RK_FUNC_2 &pcfg_pull_up>;
> +					<2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi5_rx: spi5-rx {
> 				rockchip,pins =
> -					<2 20 RK_FUNC_2 &pcfg_pull_up>;
> +					<2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>;
> 			};
> 			spi5_tx: spi5-tx {
> 				rockchip,pins =
> -					<2 21 RK_FUNC_2 &pcfg_pull_up>;
> +					<2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>;
> +			};
> +		};
> +
> +		tsadc {
> +			otp_gpio: otp-gpio {
> +				rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
> +			};
> +
> +			otp_out: otp-out {
> +				rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart0 {
> 			uart0_xfer: uart0-xfer {
> 				rockchip,pins =
> -					<2 16 RK_FUNC_1 &pcfg_pull_up>,
> -					<2 17 RK_FUNC_1 &pcfg_pull_none>;
> +					<2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>,
> +					<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 
> 			uart0_cts: uart0-cts {
> 				rockchip,pins =
> -					<2 18 RK_FUNC_1 &pcfg_pull_none>;
> +					<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 
> 			uart0_rts: uart0-rts {
> 				rockchip,pins =
> -					<2 19 RK_FUNC_1 &pcfg_pull_none>;
> +					<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart1 {
> 			uart1_xfer: uart1-xfer {
> 				rockchip,pins =
> -					<3 12 RK_FUNC_2 &pcfg_pull_up>,
> -					<3 13 RK_FUNC_2 &pcfg_pull_none>;
> +					<3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>,
> +					<3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart2a {
> 			uart2a_xfer: uart2a-xfer {
> 				rockchip,pins =
> -					<4 8 RK_FUNC_2 &pcfg_pull_up>,
> -					<4 9 RK_FUNC_2 &pcfg_pull_none>;
> +					<4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>,
> +					<4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart2b {
> 			uart2b_xfer: uart2b-xfer {
> 				rockchip,pins =
> -					<4 16 RK_FUNC_2 &pcfg_pull_up>,
> -					<4 17 RK_FUNC_2 &pcfg_pull_none>;
> +					<4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>,
> +					<4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart2c {
> 			uart2c_xfer: uart2c-xfer {
> 				rockchip,pins =
> -					<4 19 RK_FUNC_1 &pcfg_pull_up>,
> -					<4 20 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>,
> +					<4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart3 {
> 			uart3_xfer: uart3-xfer {
> 				rockchip,pins =
> -					<3 14 RK_FUNC_2 &pcfg_pull_up>,
> -					<3 15 RK_FUNC_2 &pcfg_pull_none>;
> +					<3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>,
> +					<3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 
> 			uart3_cts: uart3-cts {
> 				rockchip,pins =
> -					<3 18 RK_FUNC_2 &pcfg_pull_none>;
> +					<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 
> 			uart3_rts: uart3-rts {
> 				rockchip,pins =
> -					<3 19 RK_FUNC_2 &pcfg_pull_none>;
> +					<3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uart4 {
> 			uart4_xfer: uart4-xfer {
> 				rockchip,pins =
> -					<1 7 RK_FUNC_1 &pcfg_pull_up>,
> -					<1 8 RK_FUNC_1 &pcfg_pull_none>;
> +					<1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>,
> +					<1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		uarthdcp {
> 			uarthdcp_xfer: uarthdcp-xfer {
> 				rockchip,pins =
> -					<4 21 RK_FUNC_2 &pcfg_pull_up>,
> -					<4 22 RK_FUNC_2 &pcfg_pull_none>;
> +					<4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>,
> +					<4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		pwm0 {
> 			pwm0_pin: pwm0-pin {
> 				rockchip,pins =
> -					<4 18 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 
> 			vop0_pwm_pin: vop0-pwm-pin {
> 				rockchip,pins =
> -					<4 18 RK_FUNC_2 &pcfg_pull_none>;
> +					<4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		pwm1 {
> 			pwm1_pin: pwm1-pin {
> 				rockchip,pins =
> -					<4 22 RK_FUNC_1 &pcfg_pull_none>;
> +					<4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 
> 			vop1_pwm_pin: vop1-pwm-pin {
> 				rockchip,pins =
> -					<4 18 RK_FUNC_3 &pcfg_pull_none>;
> +					<4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		pwm2 {
> 			pwm2_pin: pwm2-pin {
> 				rockchip,pins =
> -					<1 19 RK_FUNC_1 &pcfg_pull_none>;
> +					<1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		pwm3a {
> 			pwm3a_pin: pwm3a-pin {
> 				rockchip,pins =
> -					<0 6 RK_FUNC_1 &pcfg_pull_none>;
> +					<0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
> 			};
> 		};
> 
> 		pwm3b {
> 			pwm3b_pin: pwm3b-pin {
> 				rockchip,pins =
> -					<1 14 RK_FUNC_1 &pcfg_pull_none>;
> +					<1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
> +			};
> +		};
> +
> +		hdmi {
> +			hdmi_i2c_xfer: hdmi-i2c-xfer {
> +				rockchip,pins =
> +					<4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
> +					<4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
> +			};
> +
> +			hdmi_cec: hdmi-cec {
> +				rockchip,pins =
> +					<4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
> +			};
> +		};
> +
> +		pcie {
> +			pcie_clkreqn: pci-clkreqn {
> +				rockchip,pins =
> +					<2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>;
> +			};
> +
> +			pcie_clkreqnb: pci-clkreqnb {
> +				rockchip,pins =
> +					<4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
> +			};
> +
> +			pcie_clkreqn_cpm: pci-clkreqn-cpm {
> +				rockchip,pins =
> +					<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
> +			};
> +
> +			pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
> +				rockchip,pins =
> +					<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> 			};
> 		};
> +
> 	};
> };
> diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
> index ecb76c7..0798287 100644
> --- a/include/dt-bindings/pinctrl/rockchip.h
> +++ b/include/dt-bindings/pinctrl/rockchip.h
> @@ -4,7 +4,7 @@
>  * Copyright (c) 2013 MundoReader S.L.
>  * Author: Heiko Stuebner <heiko at sntech.de>
>  *
> - * SPDX-License-Identifier:	GPL-2.0+
> + * SPDX-License-Identifier:    GPL-2.0+
>  */
> 
> #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
> @@ -17,6 +17,39 @@
> #define RK_GPIO4	4
> #define RK_GPIO6	6
> 
> +#define RK_PA0		0
> +#define RK_PA1		1
> +#define RK_PA2		2
> +#define RK_PA3		3
> +#define RK_PA4		4
> +#define RK_PA5		5
> +#define RK_PA6		6
> +#define RK_PA7		7
> +#define RK_PB0		8
> +#define RK_PB1		9
> +#define RK_PB2		10
> +#define RK_PB3		11
> +#define RK_PB4		12
> +#define RK_PB5		13
> +#define RK_PB6		14
> +#define RK_PB7		15
> +#define RK_PC0		16
> +#define RK_PC1		17
> +#define RK_PC2		18
> +#define RK_PC3		19
> +#define RK_PC4		20
> +#define RK_PC5		21
> +#define RK_PC6		22
> +#define RK_PC7		23
> +#define RK_PD0		24
> +#define RK_PD1		25
> +#define RK_PD2		26
> +#define RK_PD3		27
> +#define RK_PD4		28
> +#define RK_PD5		29
> +#define RK_PD6		30
> +#define RK_PD7		31
> +
> #define RK_FUNC_GPIO	0
> #define RK_FUNC_1	1
> #define RK_FUNC_2	2
> diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h
> new file mode 100644
> index 0000000..168b3bf
> --- /dev/null
> +++ b/include/dt-bindings/power/rk3399-power.h
> @@ -0,0 +1,53 @@
> +#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
> +#define __DT_BINDINGS_POWER_RK3399_POWER_H__
> +
> +/* VD_CORE_L */
> +#define RK3399_PD_A53_L0	0
> +#define RK3399_PD_A53_L1	1
> +#define RK3399_PD_A53_L2	2
> +#define RK3399_PD_A53_L3	3
> +#define RK3399_PD_SCU_L		4
> +
> +/* VD_CORE_B */
> +#define RK3399_PD_A72_B0	5
> +#define RK3399_PD_A72_B1	6
> +#define RK3399_PD_SCU_B		7
> +
> +/* VD_LOGIC */
> +#define RK3399_PD_TCPD0		8
> +#define RK3399_PD_TCPD1		9
> +#define RK3399_PD_CCI		10
> +#define RK3399_PD_CCI0		11
> +#define RK3399_PD_CCI1		12
> +#define RK3399_PD_PERILP	13
> +#define RK3399_PD_PERIHP	14
> +#define RK3399_PD_VIO		15
> +#define RK3399_PD_VO		16
> +#define RK3399_PD_VOPB		17
> +#define RK3399_PD_VOPL		18
> +#define RK3399_PD_ISP0		19
> +#define RK3399_PD_ISP1		20
> +#define RK3399_PD_HDCP		21
> +#define RK3399_PD_GMAC		22
> +#define RK3399_PD_EMMC		23
> +#define RK3399_PD_USB3		24
> +#define RK3399_PD_EDP		25
> +#define RK3399_PD_GIC		26
> +#define RK3399_PD_SD		27
> +#define RK3399_PD_SDIOAUDIO	28
> +#define RK3399_PD_ALIVE		29
> +
> +/* VD_CENTER */
> +#define RK3399_PD_CENTER	30
> +#define RK3399_PD_VCODEC	31
> +#define RK3399_PD_VDU		32
> +#define RK3399_PD_RGA		33
> +#define RK3399_PD_IEP		34
> +
> +/* VD_GPU */
> +#define RK3399_PD_GPU		35
> +
> +/* VD_PMU */
> +#define RK3399_PD_PMU		36
> +
> +#endif
> -- 
> 1.9.1
> 



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