[U-Boot] [PATCH v1 2/3] rockchip: video: Add mipi display support for rk3288

[Eric Gao]

Because rk3288 and rk3399 use the same mipi dsi controller and phy with
only a few difference in grf register. So we share the mipi driver, and
handle the difference.

Signed-off-by: Eric Gao <eric.gao at rock-chips.com>

---

Changes in v1:
-Make a different configuration for rk3288.

 drivers/video/rockchip/rk_mipi.c | 54 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 48 insertions(+), 6 deletions(-)

diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index ab131cd..9c29308 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -20,9 +20,13 @@
 #include <linux/kernel.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3399.h>
-#include <asm/arch/grf_rk3399.h>
 #include <asm/arch/rockchip_mipi_dsi.h>
-#include <dt-bindings/clock/rk3288-cru.h>
+
+#ifdef CONFIG_ROCKCHIP_RK3399
+	#include <asm/arch/grf_rk3399.h>
+#elif CONFIG_ROCKCHIP_RK3288
+	#include <asm/arch/grf_rk3288.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,7 +45,11 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 struct rk_mipi_priv {
 	void __iomem *regs;
+	#ifdef CONFIG_ROCKCHIP_RK3399
 	struct rk3399_grf_regs *grf;
+	#elif CONFIG_ROCKCHIP_RK3288
+	struct rk3288_grf *grf;
+	#endif
 	struct udevice *panel;
 	struct mipi_dsi *dsi;
 	u32 ref_clk;
@@ -118,18 +126,33 @@ static int rk_mipi_dsi_enable(struct udevice *dev,
 	/* Select the video source */
 	switch (disp_uc_plat->source_id) {
 	case VOP_B:
+		#ifdef CONFIG_ROCKCHIP_RK3399
 		rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
-			     GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
-		 break;
+			     GRF_DSI0_VOP_SEL_B
+			     << GRF_DSI0_VOP_SEL_SHIFT);
+		#elif CONFIG_ROCKCHIP_RK3288
+		rk_clrsetreg(&priv->grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
+			     RK3288_DSI0_LCDC_SEL_BIG
+			     << RK3288_DSI0_LCDC_SEL_SHIFT);
+		#endif
+		break;
 	case VOP_L:
+		#ifdef CONFIG_ROCKCHIP_RK3399
 		rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
-			     GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
-		 break;
+			     GRF_DSI0_VOP_SEL_L
+			     << GRF_DSI0_VOP_SEL_SHIFT);
+		#elif CONFIG_ROCKCHIP_RK3288
+		rk_clrsetreg(&priv->grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK,
+			     RK3288_DSI0_LCDC_SEL_LIT
+			     << RK3288_DSI0_LCDC_SEL_SHIFT);
+		#endif
+		break;
 	default:
 		 debug("%s: Invalid VOP id\n", __func__);
 		 return -EINVAL;
 	}
 
+	#ifdef CONFIG_ROCKCHIP_RK3399
 	/* Set Controller as TX mode */
 	val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
 	rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
@@ -142,6 +165,24 @@ static int rk_mipi_dsi_enable(struct udevice *dev,
 	val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
 	rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
 
+	#elif CONFIG_ROCKCHIP_RK3288
+	/* Set Controller as TX mode */
+	val = RK3288_DPHY_TX0_RXMODE_DIS << RK3288_DPHY_TX0_RXMODE_SHIFT;
+	rk_clrsetreg(&priv->grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val);
+
+	/* Exit tx stop mode */
+	val |= RK3288_DPHY_TX0_TXSTOPMODE_EN
+	       << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT;
+	rk_clrsetreg(&priv->grf->soc_con8,
+		     RK3288_DPHY_TX0_TXSTOPMODE_MASK, val);
+
+	/* Disable turnequest */
+	val |= RK3288_DPHY_TX0_TURNREQUEST_EN
+	       << RK3288_DPHY_TX0_TURNREQUEST_SHIFT;
+	rk_clrsetreg(&priv->grf->soc_con8,
+		     RK3288_DPHY_TX0_TURNREQUEST_MASK, val);
+	#endif
+
 	/* Set Display timing parameter */
 	rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
 	rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
@@ -477,6 +518,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {
 
 static const struct udevice_id rk_mipi_dsi_ids[] = {
 	{ .compatible = "rockchip,rk3399_mipi_dsi" },
+	{ .compatible = "rockchip,rk3288_mipi_dsi" },
 	{ }
 };
 
-- 
1.9.1