[U-Boot] [PATCH 5/8] armv8: Add workaround for USB erratum A-009798

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta at freescale.com>

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 22 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  5 +++++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 30 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1544eaa..27eb8fb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,6 +28,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+       u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+       val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+       val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+       u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -200,6 +219,8 @@ void fsl_lsch3_early_init_f(void)
 #endif
 	erratum_a008514();
 	erratum_a008336();
+	erratum_a009008();
+	erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -471,6 +492,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009929();
 	erratum_a009660();
 	erratum_a010539();
+	erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8f66938..e66253f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -113,6 +113,7 @@
 #define EPU_EPGCR		0x700060000ULL
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009798
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5210b8c..5763586 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,6 +198,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_USB3PRM1CR_USB2           0x07C
+#define SCFG_USB3PRM1CR_USB3           0x088
+#define USB_TXVREFTUNE                 0x9
+#define USB_SQRXTUNE                   0xFC7FFFFF
+
 	u32     devdisr2;       /* Device disable control 2 */
 	u32     devdisr3;       /* Device disable control 3 */
 	u32     devdisr4;       /* Device disable control 4 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e181ef2..281f0ee 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,8 @@
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
+#define USB_TXVREFTUNE                 0x9
+#define USB_SQRXTUNE                   0xFC7FFFFF
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324