[U-Boot] [PATCH 1/8] armv8: Add workaround for USB erratum A-009008

Ran Wang ran.wang_1 at nxp.com
Wed Aug 2 09:55:22 UTC 2017


Hello Sir,
    May I know the review result for this patch set? Thank you.
BR
Ran

> -----Original Message-----
> From: Ran Wang [mailto:ran.wang_1 at nxp.com]
> Sent: Monday, July 10, 2017 10:24 AM
> To: Albert Aribaud <albert.u.boot at aribaud.net>; York Sun <york.sun at nxp.com>;
> Suresh Gupta <suresh.bhagat at nxp.com>
> Cc: Simon Glass <sjg at chromium.org>; Sriram Dash <sriram.dash at nxp.com>;
> Rajesh Bhagat <rajesh.bhagat at nxp.com>; Andy Tang <andy.tang at nxp.com>;
> Shengzhou Liu <shengzhou.liu at nxp.com>; Priyanka Jain
> <priyanka.jain at nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>; open list <u-boot at lists.denx.de>; Ran Wang
> <ran.wang_1 at nxp.com>
> Subject: [PATCH 1/8] armv8: Add workaround for USB erratum A-009008
> 
> USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with
> the default value at many corners, particularly at a high temperature
> 
> Optimal eye at TXREFTUNE value to 1001 is observed, change set the same
> value.
> 
> Signed-off-by: Ran Wang <ran.wang_1 at nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 25
> ++++++++++++++++++++++
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6
> ++++++  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>  4 files changed, 39 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index d8b285d..eebfcfe 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -22,6 +22,7 @@ config ARCH_LS1043A
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_A010315
>  	select SYS_FSL_ERRATUM_A010539
> +	select SYS_FSL_ERRATUM_A009008
>  	select SYS_FSL_HAS_DDR3
>  	select SYS_FSL_HAS_DDR4
>  	select ARCH_EARLY_INIT_R
> @@ -42,6 +43,7 @@ config ARCH_LS1046A
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_A010165
>  	select SYS_FSL_ERRATUM_A010539
> +	select SYS_FSL_ERRATUM_A009008
>  	select SYS_FSL_HAS_DDR4
>  	select SYS_FSL_SRDS_2
>  	select ARCH_EARLY_INIT_R
> @@ -77,6 +79,7 @@ config ARCH_LS2080A
>  	select SYS_FSL_ERRATUM_A009942
>  	select SYS_FSL_ERRATUM_A010165
>  	select SYS_FSL_ERRATUM_A009203
> +	select SYS_FSL_ERRATUM_A009008
>  	select ARCH_EARLY_INIT_R
>  	select BOARD_EARLY_INIT_F
> 
> @@ -220,6 +223,10 @@ config SYS_FSL_ERRATUM_A010315  config
> SYS_FSL_ERRATUM_A010539
>  	bool "Workaround for PIN MUX erratum A010539"
> 
> +config SYS_FSL_ERRATUM_A009008
> +	bool "Workaround for USB PHY erratum A009008"
> +
> +
>  config MAX_CPUS
>  	int "Maximum number of CPUs permitted for Layerscape"
>  	default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 0943e83..a91f85e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -52,6 +52,29 @@ bool soc_has_aiop(void)
>  	return false;
>  }
> 
> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> +	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> +	u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
> +	val &= ~(0xF << 6);
> +	scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4,
> val|(USB_TXVREFTUNE << 6));
> +	val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
> +	val &= ~(0xF << 6);
> +	scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4,
> val|(USB_TXVREFTUNE << 6));
> +	val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
> +	val &= ~(0xF << 6);
> +	scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4,
> val|(USB_TXVREFTUNE <<
> +6)); #elif defined(CONFIG_ARCH_LS2080A)
> +	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> +	u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
> +	val &= ~(0xF << 6);
> +	scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE <<
> 6));
> +#endif #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ }
> +
>  #if defined(CONFIG_FSL_LSCH3)
>  /*
>   * This erratum requires setting a value to eddrtqcr1 to @@ -198,6 +221,7 @@
> void fsl_lsch3_early_init_f(void)  #endif
>  	erratum_a008514();
>  	erratum_a008336();
> +	erratum_a009008();
>  #ifdef CONFIG_CHAIN_OF_TRUST
>  	/* In case of Secure Boot, the IBR configures the SMMU
>  	* to allow only Secure transactions.
> @@ -473,6 +497,7 @@ void fsl_lsch2_early_init_f(void)
>  	erratum_a009929();
>  	erratum_a009660();
>  	erratum_a010539();
> +	erratum_a009008();
>  }
>  #endif
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 8ad199f..62d7046 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -337,6 +337,12 @@ struct ccsr_gur {
>  #define SCFG_USBPWRFAULT_USB2_SHIFT	2
>  #define SCFG_USBPWRFAULT_USB1_SHIFT	0
> 
> +#define SCFG_BASE			0x01570000
> +#define SCFG_USB3PRM1CR_USB1		0x070
> +#define SCFG_USB3PRM1CR_USB2		0x07C
> +#define SCFG_USB3PRM1CR_USB3		0x088
> +#define USB_TXVREFTUNE			0x9
> +
>  #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
>  #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
>  #define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 59410aa..c622ee5 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -133,6 +133,7 @@
>  #define SCFG_BASE		0x01fc0000
>  #define SCFG_USB3PRM1CR			0x000
>  #define SCFG_USB3PRM1CR_INIT		0x27672b2a
> +#define USB_TXVREFTUNE			0x9
>  #define SCFG_QSPICLKCTLR	0x10
> 
>  #define TP_ITYP_AV		0x00000001	/* Initiator available */
> --
> 2.1.0.27.g96db324



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