[U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before new spi operation

[Jagan Teki]

On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta <suresh.gupta at nxp.com> wrote:
> It is recommended to check either controller is free to take
> new spi action. The IP_ACC and AHB_ACC bits indicates that
> the controller is busy in IP or AHB mode respectively.
> And the BUSY bit indicates that the controller is currently
> busy handling a transaction to an external flash device
>
> Signed-off-by: Suresh Gupta <suresh.gupta at nxp.com>
> ---
>  drivers/spi/fsl_qspi.c | 26 ++++++++++++++++++++++++++
>  drivers/spi/fsl_qspi.h |  4 ++++
>  2 files changed, 30 insertions(+)
>
> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
> index 1dfa89a..69e9712 100644
> --- a/drivers/spi/fsl_qspi.c
> +++ b/drivers/spi/fsl_qspi.c
> @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)
>  #endif
>  }
>
> +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv)
> +{
> +       u32 sr;
> +       u32 retry = 5;
> +
> +       do {
> +               sr = qspi_read32(priv->flags, &priv->regs->sr);
> +               if ((sr & QSPI_SR_BUSY_MASK) ||

Does this bit need? we can check the busy-state with AHB_ACC and IP_ACC

> +                   (sr & QSPI_SR_AHB_ACC_MASK) ||
> +                   (sr & QSPI_SR_IP_ACC_MASK)) {
> +                       debug("The controller is busy, sr = 0x%x\n", sr);
> +                       udelay(1);
> +               } else {
> +                       break;
> +               }
> +       } while (--retry);

These retry and infine loop doesn't seems OK, how about using wait_for_bit?

> +
> +       return (sr & QSPI_SR_BUSY_MASK) ||
> +               (sr & QSPI_SR_AHB_ACC_MASK) || (sr & QSPI_SR_IP_ACC_MASK);

I didn't understand why these bits need to return? and when will the
LUT trigger?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.