[U-Boot] [PATCH] mtd: nand: zynq: Add a config option to use timing values set by FSBL

[Michal Simek]

On 25.8.2017 09:15, Wilson Lee wrote:
> From: Jeff Westfahl <jeff.westfahl at ni.com>
> 
> In legacy method, FSBL was used to configure the HW setting such as
> NAND timing. Hence, adding a config option in Zynq NAND driver for the
> compability of device that using FSBL instead of U-boot SPL.
> 
> This commit is to add config option CONFIG_NAND_ZYNQ_USE_FSBL_TIMINGS
> that allow NAND driver use timing values set by the FSBL, instead of
> the hard-coded values in the Zynq NAND driver.
> 
> Signed-off-by: Jeff Westfahl <jeff.westfahl at ni.com>
> Signed-off-by: Wilson Lee <wilson.lee at ni.com>
> Cc: Joe Hershberger <joe.hershberger at ni.com>
> Cc: Keng Soon Cheah <keng.soon.cheah at ni.com>
> Cc: Chen Yee Chew <chen.yee.chew at ni.com>
> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu at xilinx.com>
> Cc: Michal Simek <michal.simek at xilinx.com>
> Cc: Scott Wood <oss at buserror.net>
> ---
> 
>  drivers/mtd/nand/Kconfig     | 6 ++++++
>  drivers/mtd/nand/zynq_nand.c | 5 +++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 71d678f..44d6aa0 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -121,6 +121,12 @@ config NAND_ZYNQ
>  	  This enables Nand driver support for Nand flash controller
>  	  found on Zynq SoC.
>  
> +config NAND_ZYNQ_USE_FSBL_TIMINGS

it is not only fsbl which can set it up. That's why please rename this
config option.

> +	bool "Enable use of FSBL timing for NAND"
> +	depends on NAND_ZYNQ
> +	help
> +	  This enabled the use of FSBL timing for NAND flash controller.
> +
>  comment "Generic NAND options"
>  
>  # Enhance depends when converting drivers to Kconfig which use this config
> diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
> index 484f1bb..f292531 100644
> --- a/drivers/mtd/nand/zynq_nand.c
> +++ b/drivers/mtd/nand/zynq_nand.c
> @@ -35,6 +35,8 @@
>  				(0x1 << 4)   |	/* Clear interrupt */ \
>  				(0x1 << 6))	/* Disable ECC interrupt */
>  
> +#ifndef CONFIG_NAND_ZYNQ_USE_FSBL_TIMINGS
> +
>  /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
>  #define ZYNQ_NAND_SET_CYCLES	((0x2 << 20) |	/* t_rr from nand_cycles */ \
>  				(0x2 << 17)  |	/* t_ar from nand_cycles */ \
> @@ -43,6 +45,7 @@
>  				(0x2 << 8)   |	/* t_rea from nand_cycles */ \
>  				(0x5 << 4)   |	/* t_wc from nand_cycles */ \
>  				(0x5 << 0))	/* t_rc from nand_cycles */
> +#endif
>  
>  
>  #define ZYNQ_NAND_DIRECT_CMD	((0x4 << 23) |	/* Chip 0 from interface 1 */ \
> @@ -257,8 +260,10 @@ static int zynq_nand_init_nand_flash(int option)
>  
>  	/* disable interrupts */
>  	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
> +#ifndef CONFIG_NAND_ZYNQ_USE_FSBL_TIMINGS
>  	/* Initialize the NAND interface by setting cycles and operation mode */
>  	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
> +#endif
>  	if (option & NAND_BUSWIDTH_16)
>  		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
>  	else
> 

Siva: is this even needed to setup these cycles or simple we are taking
it from psu_init?

Thanks,
Michal