[U-Boot] [PATCH] serial: serial_sh: take into account port->clk_mode for SH7785/7786

[Thomas Petazzoni]

In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a,
which means bits CKE1/CKE0 have the value 10b. This tells the SCIF
that the "External clock/SCIF_SCK pin functions as clock input".

However, this is not the case in all designs, and it's the purpose of
the clk_mode = EXT_CLK to indicate such a setting.

In order for the serial_sh driver to work on a SH7786 platform that
does not use SCIF_SCK as a clock input, we have to adjust the
SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to
what is done for other SH platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 drivers/serial/serial_sh.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 4d27122..d7bbd1a 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -184,7 +184,8 @@ struct uart_port {
 # define SCSPTR4	0xffee0024	/* 16 bit SCIF */
 # define SCSPTR5	0xffef0024	/* 16 bit SCIF */
 # define SCIF_ORER	0x0001		/* Overrun error bit */
-# define SCSCR_INIT(port)	0x3a	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+# define SCSCR_INIT(port)	(port->clk_mode == EXT_CLK ? 0x3a : 0x38)
+				/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SH7201) || \
 	defined(CONFIG_CPU_SH7203) || \
 	defined(CONFIG_CPU_SH7206) || \
-- 
2.9.4