[U-Boot] [PATCH 4/4] ARM: dts: uniphier: update PXs3 SoC/board DT
Masahiro Yamada
yamada.masahiro at socionext.com
Tue Aug 29 03:20:53 UTC 2017
Support PXs3 SoC and its reference development board.
Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com>
---
arch/arm/dts/uniphier-pxs3-ref.dts | 21 ++++--
arch/arm/dts/uniphier-pxs3.dtsi | 127 ++++++++++++++++++++++++-------------
2 files changed, 98 insertions(+), 50 deletions(-)
diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts
index cb1eef43c464..d65f746a3f9d 100644
--- a/arch/arm/dts/uniphier-pxs3-ref.dts
+++ b/arch/arm/dts/uniphier-pxs3-ref.dts
@@ -4,13 +4,12 @@
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro at socionext.com>
*
- * SPDX-License-Identifier: GPL-2.0+ X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
-/include/ "uniphier-pxs3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
+#include "uniphier-pxs3.dtsi"
+#include "uniphier-support-card.dtsi"
/ {
model = "UniPhier PXs3 Reference Board";
@@ -39,7 +38,7 @@
};
ðsc {
- interrupts = <0 48 4>;
+ interrupts = <0 52 4>;
};
&serial0 {
@@ -49,3 +48,15 @@
&i2c0 {
status = "okay";
};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index cdf7f9005f73..8615ba0bc771 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -4,46 +4,10 @@
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro at socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;
/ {
compatible = "socionext,uniphier-pxs3";
@@ -76,28 +40,74 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu at 2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x002>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu at 3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x003>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+ };
+
+ cluster0_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp-866667000 {
+ opp-hz = /bits/ 64 <866667000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ clock-latency-ns = <300>;
};
};
@@ -172,6 +182,22 @@
clock-frequency = <58820000>;
};
+ gpio: gpio at 55000000 {
+ compatible = "socionext,uniphier-pxs3-gpio";
+ reg = <0x55000000 0x200>;
+ interrupt-parent = <&aidet>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 0>,
+ <&pinctrl 96 0 0>,
+ <&pinctrl 160 0 0>;
+ gpio-ranges-group-names = "gpio_range0",
+ "gpio_range1",
+ "gpio_range2";
+ };
+
i2c0: i2c at 58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
@@ -205,6 +231,8 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
@@ -251,7 +279,7 @@
sdctrl at 59810000 {
compatible = "socionext,uniphier-pxs3-sdctrl",
"simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
+ reg = <0x59810000 0x400>;
sd_clk: clock {
compatible = "socionext,uniphier-pxs3-sd-clock";
@@ -282,7 +310,6 @@
emmc: sdhc at 5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
- status = "disabled";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
@@ -291,6 +318,11 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-mmc-highspeed = <2>;
+ cdns,phy-input-delay-mmc-ddr = <3>;
+ cdns,phy-dll-delay-sdclk = <21>;
+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
sd: sdhc at 5a400000 {
@@ -317,9 +349,11 @@
};
};
- aidet at 5fc20000 {
- compatible = "simple-mfd", "syscon";
+ aidet: aidet at 5fc20000 {
+ compatible = "socionext,uniphier-pxs3-aidet";
reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gic: interrupt-controller at 5fe00000 {
@@ -345,10 +379,14 @@
compatible = "socionext,uniphier-pxs3-reset";
#reset-cells = <1>;
};
+
+ watchdog {
+ compatible = "socionext,uniphier-wdt";
+ };
};
nand: nand at 68000000 {
- compatible = "socionext,denali-nand-v5b";
+ compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
@@ -356,9 +394,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
- nand-ecc-strength = <8>;
};
};
};
-/include/ "uniphier-pinctrl.dtsi"
+#include "uniphier-pinctrl.dtsi"
--
2.7.4
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