[U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008

[Ran Wang]

> -----Original Message-----
> From: York Sun
> Sent: Thursday, August 31, 2017 2:07 AM
> To: Ran Wang <ran.wang_1 at nxp.com>; open list <u-boot at lists.denx.de>
> Cc: Suresh Gupta <suresh.bhagat at nxp.com>; Sriram Dash
> <sriram.dash at nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha at nxp.com>; Simon Glass <sjg at chromium.org>; Rajesh
> Bhagat <rajesh.bhagat at nxp.com>; Andy Tang <andy.tang at nxp.com>; Priyanka
> Jain <priyanka.jain at nxp.com>
> Subject: Re: [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008
> 
> On 08/28/2017 02:32 AM, Ran Wang wrote:
> > USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram
> > fails with the default value at many corners, particularly at a high
> > temperature
> >
> > Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same
> > value.
> >
> > Signed-off-by: Ran Wang <ran.wang_1 at nxp.com>
> > ---
> > Change in v4:
> > 	Change 1001 to 0x9 in the commit message to match the code.
> > 	Clean up the math in set_usb_txvreftune().
> > 	Rename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.
> >
> > Change in v3:
> > 	Use inline function to make code cleaner.
> >
> > Change in v2:
> > 	In function erratum_a009008():
> > 	1.Put a blank line after variable declaration.
> > 	2.Move common code together.
> >
> >   arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  7 ++++++
> >   arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 26
> ++++++++++++++++++++++
> >   .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 +++++
> >   .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> >   4 files changed, 40 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > index cdeef26fe5..d8936a4334 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > @@ -22,6 +22,7 @@ config ARCH_LS1043A
> >   	select SYS_FSL_ERRATUM_A009942
> >   	select SYS_FSL_ERRATUM_A010315
> >   	select SYS_FSL_ERRATUM_A010539
> > +	select SYS_FSL_ERRATUM_A009008
> >   	select SYS_FSL_HAS_DDR3
> >   	select SYS_FSL_HAS_DDR4
> >   	select ARCH_EARLY_INIT_R
> > @@ -44,6 +45,7 @@ config ARCH_LS1046A
> >   	select SYS_FSL_ERRATUM_A009942
> >   	select SYS_FSL_ERRATUM_A010165
> >   	select SYS_FSL_ERRATUM_A010539
> > +	select SYS_FSL_ERRATUM_A009008
> >   	select SYS_FSL_HAS_DDR4
> >   	select SYS_FSL_SRDS_2
> >   	select ARCH_EARLY_INIT_R
> > @@ -80,6 +82,7 @@ config ARCH_LS2080A
> >   	select SYS_FSL_ERRATUM_A009942
> >   	select SYS_FSL_ERRATUM_A010165
> >   	select SYS_FSL_ERRATUM_A009203
> > +	select SYS_FSL_ERRATUM_A009008
> >   	select ARCH_EARLY_INIT_R
> >   	select BOARD_EARLY_INIT_F
> >
> > @@ -223,6 +226,10 @@ config SYS_FSL_ERRATUM_A010315
> >   config SYS_FSL_ERRATUM_A010539
> >   	bool "Workaround for PIN MUX erratum A010539"
> >
> > +config SYS_FSL_ERRATUM_A009008
> > +	bool "Workaround for USB PHY erratum A009008"
> > +
> > +
> >   config MAX_CPUS
> >   	int "Maximum number of CPUs permitted for Layerscape"
> >   	default 4 if ARCH_LS1043A
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 639e9d2ddc..52a7abd13c 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -52,6 +52,30 @@ bool soc_has_aiop(void)
> >   	return false;
> >   }
> >
> > +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
> > +{
> > +	u32 val;
> > +
> > +	val = scfg_in32(scfg + offset / 4);
> > +	val &= ~(0xF << 6);
> > +	val |= SCFG_USB_TXVREFTUNE << 6;
> > +	scfg_out32(scfg + offset / 4, val);
> > +}
> 
> As Marek suggested, can we use this?
> 
> +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) {
> +	scfg_clrsetbits_32(scfg + offset / 4,
> +			   0xF << 6,
> +			   SCFG_USB_TXVREFTUNE << 6);
> +}
> 
> This means a new macro is added in soc.h.
OK, will work out v5 and re-test, thanks for sample code.
> 
> I still prefer to keep "inline" here to avoid using stack frame for this simple but
> repeated call.
Agree, 
> 
> York