[U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when enabling new timing mode

Maxime Ripard maxime.ripard at free-electrons.com
Thu Aug 31 14:04:41 UTC 2017

On Thu, Aug 31, 2017 at 09:57:48PM +0800, Chen-Yu Tsai wrote:
> When enabling the new mmc timing mode, we inadvertently clear all the
> remaining bits in the new timing mode register. The bits cleared
> include a default phase delay on the output clock. The BSP kernel
> states that the default values are supposed to be used. Clearing them
> results in decreased performance or transfer errors on some boards.
> Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
> Signed-off-by: Chen-Yu Tsai <wens at csie.org>

Acked-by: Maxime Ripard <maxime.ripard at free-electrons.com>


Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
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