[U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg registers

[Calvin Johnson]

Hi Poonam,

> -----Original Message-----
> From: Poonam Aggrwal
> Sent: Friday, November 24, 2017 11:25 AM
> To: Calvin Johnson <calvin.johnson at nxp.com>; u-boot at lists.denx.de
> Cc: joe.hershberger at ni.com; Anji Jagarlmudi <anji.jagarlmudi at nxp.com>
> Subject: RE: [U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg
> registers
> 
> Hello Calvin
> 
> Please find few comments inline.
> 
> Regards
> Poonam
> 
> > -----Original Message-----
> > From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Calvin
> > Johnson
> > Sent: Monday, October 09, 2017 2:42 PM
> > To: u-boot at lists.denx.de
> > Cc: joe.hershberger at ni.com; Anji Jagarlmudi <anji.jagarlmudi at nxp.com>
> > Subject: [U-Boot] [PATCH 7/9] armv8: fsl-lsch2: configure pfe's scfg & dcfg
> > registers
> Reword: configure Qos, cacheable...attributes for PFE by programming SCFG
> and DFCG registers
> >
> > Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg registers of pfe.
> Consider to reword for more explanation
> Configure "xyz cacheable attributes, via scfg
> PFE QoS settings configured as  .... via scfg
> dcfg ??
> >
> > Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
> > Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c        | 18 ++++++++++++++++++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h |  3 +++
> >  2 files changed, 21 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 5c429d4..c6815f3 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -577,6 +577,24 @@ int setup_chip_volt(void)
> >  	return 0;
> >  }
> >
> > +#ifdef CONFIG_FSL_PFE
> > +void init_pfe_scfg_dcfg_regs(void)
> > +{
> > +	struct ccsr_scfg *scfg = (struct ccsr_scfg
> > *)CONFIG_SYS_FSL_SCFG_ADDR;
> > +
> > +	out_be32(&scfg->pfeasbcr,
> > +		 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
> > +	out_be32(&scfg->pfebsbcr,
> > +		 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
> > +
> > +	/* CCI-400 QoS settings for PFE */
> This is incomplete sentence, we should also tell what settings are being
> done.
> > +	out_be32(&scfg->wr_qos1, 0x0ff00000);
> > +	out_be32(&scfg->rd_qos1, 0x0ff00000);
> Avoid hardcoding/magic numbers
> > +
> > +	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x524, 0x2000);
> Should remove hardcoded values , 0x524, 0x2000.
> 0x524 does not show up in the LS1012A RM (Rev 0). Please check once.
> Also adding one liner telling what the above settings mean will help .

Thanks for your comments. Will take care of them in v2 of the series.

Regards
Calvin