[U-Boot] [PATCH 04/15] clk: rmobile: Add R8A77995 D3 clock tables
Marek Vasut
marek.vasut at gmail.com
Thu Dec 7 14:37:01 UTC 2017
Add clock tables for R8A77995 D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas at gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
---
drivers/clk/renesas/clk-rcar-gen3.c | 167 +++++++++++++++++++++++++++++++++++-
1 file changed, 164 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index c56d52b1ce..b26bbcc59f 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -21,6 +21,7 @@
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#define CPG_RST_MODEMR 0x0060
@@ -127,6 +128,10 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+ _div_clean) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, \
+ (_parent_clean), .div = (_div_clean), 1)
/*
* Definitions of Module Clocks
@@ -155,6 +160,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_R,
+ CLK_TYPE_GEN3_PE,
CLK_TYPE_GEN3_Z2,
};
@@ -181,6 +187,11 @@ enum clk_ids {
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
+ CLK_PLL0D2,
+ CLK_PLL0D3,
+ CLK_PLL0D5,
+ CLK_PLL1D2,
+ CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
@@ -688,6 +699,128 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
};
+static const struct cpg_core_clk r8a77995_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
+ DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
+ DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
+ DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
+ DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
+ DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
+ DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
+
+ DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
+ DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+ DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+ DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
+};
+
+static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
+ DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
+ DEF_MOD("cmt3", 300, R8A77995_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77995_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77995_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77995_CLK_R),
+ DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
+ DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
+ DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A77995_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
+ DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
+ DEF_MOD("thermal", 522, R8A77995_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
+ DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
+ DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
+ DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
+ DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
+ DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
+ DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
+ DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
+ DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
+ DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
+ DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
+ DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+};
+
/*
* CPG Clock Data
*/
@@ -1024,6 +1157,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
return rate;
case CLK_TYPE_FF:
+ case CLK_TYPE_GEN3_PE: /* FIXME */
rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
__func__, __LINE__,
@@ -1109,6 +1243,7 @@ enum gen3_clk_model {
CLK_R8A7795,
CLK_R8A7796,
CLK_R8A77970,
+ CLK_R8A77995,
};
static int gen3_clk_probe(struct udevice *dev)
@@ -1154,6 +1289,16 @@ static int gen3_clk_probe(struct udevice *dev)
if (ret < 0)
return ret;
break;
+ case CLK_R8A77995:
+ priv->core_clk = r8a77995_core_clks;
+ priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks);
+ priv->mod_clk = r8a77995_mod_clks;
+ priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks);
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "renesas,r8a77995-rst");
+ if (ret < 0)
+ return ret;
+ break;
default:
return -EINVAL;
}
@@ -1172,9 +1317,11 @@ static int gen3_clk_probe(struct udevice *dev)
if (ret < 0)
return ret;
- ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
- if (ret < 0)
- return ret;
+ if (model != CLK_R8A77995) {
+ ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
+ if (ret < 0)
+ return ret;
+ }
return 0;
}
@@ -1211,6 +1358,15 @@ static struct mstp_stop_table r8a77970_mstp_table[] = {
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
+static struct mstp_stop_table r8a77995_mstp_table[] = {
+ { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
#define TSTR0 0x04
#define TSTR0_STR0 BIT(0)
@@ -1234,6 +1390,10 @@ static int gen3_clk_remove(struct udevice *dev)
tbl = r8a77970_mstp_table;
tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
break;
+ case CLK_R8A77995:
+ tbl = r8a77995_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a77995_mstp_table);
+ break;
default:
return -EINVAL;
}
@@ -1254,6 +1414,7 @@ static const struct udevice_id gen3_clk_ids[] = {
{ .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
{ .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
{ .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
+ { .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 },
{ }
};
--
2.15.0
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