[U-Boot] Linux hang
Jan Siegmund
jan.siegmund0 at hm.edu
Thu Dec 7 20:14:54 UTC 2017
Am 07.12.2017 um 20:19 schrieb Alan Tull:
> On Thu, Dec 7, 2017 at 5:00 AM, Siegmund, Jan <jan.siegmund0 at hm.edu> wrote:
>
> Hi SIegmund,
>
>> Hi all,
>> does anybody have an idea for the following problem?
>>
>> * FPGA is programmed using an overlay
>> * FPGA writes to SDRAM via the FPGA2SDRAM-bridge
>> * Linux hangs and the watchdog resets the board (the FPGA stays programmed)
>> * After the reset and boot, the FPGA is reprogrammed using the same overlay
>> * Now, the FPGA can write to the SDRAM without a problem
>>
>> The environment:
>>
>> *Board: DE0-NANO-SoC
>> *U-Boot: 2017.11
>> *Kernel: 4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch)
>>
>> The overlay:
>>
>> /dts-v1/;
>> /plugin/;
>>
>> / {
>> fragment at 0 {
>> target-path = "/soc/base_fpga_region";
>> #address-cells = <1>;
>> #size-cells = <1>;
>> __overlay__ {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
>> firmware-name = "foo_base.rbf";
>>
>> fpga-bridge at ffc25080 {
>> compatible = "altr,socfpga-fpga2sdram-bridge";
>> reg = <0xffc25080 0x4>;
>> bridge-enable = <1>;
>> };
>
> It's been a while since I've touched that bridge, but here's what I
> can think of, hope it helps.
>
> This overlay will add the bridge after programming. It looks like it
> should enable it since you have bridge-enable = <1>, so I'm not sure
> why that's not working.
>
> Would it make sense to add the f2s bridge before doing the fpga
> programming? You could add the f2s bridge in the base device tree and
> add it to your fpga-bridges list so that that bridge is enabled after
> the fpga is programmed.
Hi Alan,
this might be worth a try.
Thanks,
Jan
>
> Alan
>
>>
>> foo at ff200000 {
>> compatible= "altr,bar";
>> interrupt-parent = <&intc>;
>> interrupts = <0 40 4>;
>> };
>>
>> };
>> };
>> };
>>
>> Thanks
>
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