[U-Boot] [PATCH] powerpc: mpc85xx: Fix static TLB table for SDRAM

[York Sun]

On 12/06/2017 12:42 PM, York Sun wrote:
> Most predefined TLB tables don't have memory coherence bit set for
> SDRAM. This wasn't an issue before invalidate_dcache_range() function
> was enabled. Without the coherence bit, dcache invalidation doesn't
> automatically flush the cache. The coherence bit is already set when
> dynamic TLB table is used. For some boards with different SPL boot
> method, or with legacy fixed setting, this bit needs to be set in
> TLB files.
> 
> Signed-off-by: York Sun <york.sun at nxp.com>
> ---


Applied to u-boot-mpc85xx master.

York