[U-Boot] [RESEND PATCH v7 01/10] armv8: lsch3: Add serdes and DDR voltage setup

[York Sun]

On 11/29/2017 10:30 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
> 
> Signed-off-by: Ashish Kumar <Ashish.Kumar at nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
> ---
> Changes in v7:                                                                  
>   - Used APIs clr/set/clrsetbits_le32() for code clarity                        
> 

This version is quite good. Some nitpicks below.

<snip>

> +#endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> +	{.id = 2,
> +	 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
> +	 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
> +	},
> +#endif
> +	{.id = 0, .mask = 0, .shift = 0} /* NULL ENTRY */

An empty {} will do the same.

<snip>

> +
> +	/* For each PLL being reset, and achieved PLL lock set RST_DONE */
> +#ifdef CONFIG_SYS_FSL_SRDS_1
> +	cfg_tmp = cfg_rcwsrds1 & 0x3;
> +	do_pll_reset_done(cfg_tmp, serdes1_base);
> +#endif
> +#ifdef CONFIG_SYS_FSL_SRDS_2
> +	cfg_tmp = cfg_rcwsrds1 & 0xC;
> +	cfg_tmp >>= 2;
> +	do_pll_reset_done(cfg_tmp, serdes2_base);
> +#endif

Insert a blank line before return.

> +	return ret;
> +}
> +

York