[U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA

[Marek Vasut]

On 12/18/2017 09:44 PM, Jan Siegmund wrote:
> Hi all,

Hi,

> Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC.
> Is is possible to configure the the interface in U-Boot or SPL,

What is "the interface" ?

If you mean DRAM, then yes, the CV/AV do _not_ configure the FPGA in SPL
at all. They just configure the IOMUX/clock rings, but that's all.

> without reprogramming the FPGA? Maybe through the usage of the generated
> header files from the Quartus synthesis?
> The SDRAM controller's registers only differ in eight entries in Linux when the
> FPGA is programmed or not.
> 
> +----------+-------------+------------+----------------+
> | address  |    name     | programmed | not programmed |
> +----------+-------------+------------+----------------+
> | FFC25064 |             | 00044003   | 00044FFF       |
> | FFC25068 |             | 2C000000   | 2C03FFFF       |
> | FFC2506c |             | 00B00000   | 00B3FFFF       |
> | FFC25070 |             | 00760000   | 0076FFFF       |
> | FFC25074 |             | 00980000   | 0098FFFF       |
> | FFC25078 |             | 0005A003   | 0005AFFF       |
> | FFC2507c | portcfg     | 00000000   | 0000003F       |
> | FFC25080 | fpgaportrst | 000001FF   | 00000000       |
> +----------+-------------+------------+----------------+
> 
> The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map
> [1], so are they even intended to be configured?
> 
> Thanks
> 
> 
> 
> [1]
> https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sfo1411577380716
> 


-- 
Best regards,
Marek Vasut