[U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers
Kever Yang
kever.yang at rock-chips.com
Tue Dec 19 10:25:08 UTC 2017
Philipp,
On 12/19/2017 05:29 PM, Dr. Philipp Tomsich wrote:
> Kever,
>
> while this version has finally fixed the build errors for the rockchip-targets, it still
> causes major build failures for other target families:
> see https://travis-ci.org/ptomsich/u-boot-rockchip/builds/318128281
>
> The new driver still appears to be built for the failing boards.
I will make it depends on ARCH_ROCKCHIP.
Thanks,
- Kever
>
> Regards,
> Philipp.
>
>> On 18 Dec 2017, at 09:49, Kever Yang <kever.yang at rock-chips.com> wrote:
>>
>> From: Elaine Zhang <zhangqing at rock-chips.com>
>>
>> Create driver to support all Rockchip SoCs soft reset.
>> Example of usage:
>> i2c driver:
>> ret = reset_get_by_name(dev, "i2c", &reset_ctl);
>> if (ret) {
>> error("reset_get_by_name() failed: %d\n", ret);
>> }
>>
>> reset_assert(&reset_ctl);
>> udelay(50);
>> reset_deassert(&reset_ctl);
>>
>> i2c dts node:
>> resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
>> reset-names = "p_i2c", "i2c";
>>
>> Signed-off-by: Elaine Zhang <zhangqing at rock-chips.com>
>> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
>> ---
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - fix Kconfig more than 80 length
>> - use MACRO for reset bits in one reg
>> - use rkclr/set_reg for reg access
>> - add rockchip_reset_bind()
>> - use dev_read_addr_size() instead of fdtdec_
>>
>> drivers/reset/Kconfig | 9 +++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 143 insertions(+)
>> create mode 100644 drivers/reset/reset-rockchip.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index ce46e27..97a78d7 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -74,4 +74,13 @@ config AST2500_RESET
>> resets that are supported by watchdog. The main limitation though
>> is that some reset signals, like I2C or MISC reset multiple devices.
>>
>> +config RESET_ROCKCHIP
>> + bool "Reset controller driver for Rockchip SoCs"
>> + depends on DM_RESET && CLK
>> + default y
>> + help
>> + Support for reset controller on rockchip SoC. The main limitation
>> + though is that some reset signals, like I2C or MISC reset multiple
>> + devices.
>> +
>> endmenu
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 252cefe..7d7e080 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
>> obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
>> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
>> +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
>> diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
>> new file mode 100644
>> index 0000000..01047a2
>> --- /dev/null
>> +++ b/drivers/reset/reset-rockchip.c
>> @@ -0,0 +1,133 @@
>> +/*
>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <reset-uclass.h>
>> +#include <linux/io.h>
>> +#include <asm/arch/hardware.h>
>> +#include <dm/lists.h>
>> +/*
>> + * Each reg has 16 bits reset signal for devices
>> + * Note: Not including rk2818 and older SoCs
>> + */
>> +#define ROCKCHIP_RESET_NUM_IN_REG 16
>> +
>> +struct rockchip_reset_priv {
>> + void __iomem *base;
>> + /* Rockchip reset reg locate at cru controller */
>> + u32 reset_reg_offset;
>> + /* Rockchip reset reg number */
>> + u32 reset_reg_num;
>> +};
>> +
>> +static int rockchip_reset_request(struct reset_ctl *reset_ctl)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
>> +
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
>> + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
>> +
>> + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
>> + return -EINVAL;
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_reset_free(struct reset_ctl *reset_ctl)
>> +{
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
>> + reset_ctl->dev, reset_ctl->id);
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
>> + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
>> + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
>> +
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
>> + reset_ctl, reset_ctl->dev, reset_ctl->id,
>> + priv->base + (bank * 4));
>> +
>> + rk_setreg(priv->base + (bank * 4), BIT(offset));
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
>> + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
>> + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
>> +
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
>> + reset_ctl, reset_ctl->dev, reset_ctl->id,
>> + priv->base + (bank * 4));
>> +
>> + rk_clrreg(priv->base + (bank * 4), BIT(offset));
>> +
>> + return 0;
>> +}
>> +
>> +struct reset_ops rockchip_reset_ops = {
>> + .request = rockchip_reset_request,
>> + .free = rockchip_reset_free,
>> + .rst_assert = rockchip_reset_assert,
>> + .rst_deassert = rockchip_reset_deassert,
>> +};
>> +
>> +static int rockchip_reset_probe(struct udevice *dev)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(dev);
>> + fdt_addr_t addr;
>> + fdt_size_t size;
>> +
>> + addr = dev_read_addr_size(dev, "reg", &size);
>> + if (addr == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
>> + return -EINVAL;
>> +
>> + addr += priv->reset_reg_offset;
>> + priv->base = ioremap(addr, size);
>> +
>> + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
>> + priv->base, priv->reset_reg_offset, priv->reset_reg_num);
>> +
>> + return 0;
>> +}
>> +
>> +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
>> +{
>> + struct udevice *rst_dev;
>> + struct rockchip_reset_priv *priv;
>> + int ret;
>> +
>> + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
>> + dev_ofnode(pdev), &rst_dev);
>> + if (ret) {
>> + debug("Warning: No rockchip reset driver: ret=%d\n", ret);
>> + return ret;
>> + }
>> + priv = malloc(sizeof(struct rockchip_reset_priv));
>> + priv->reset_reg_offset = reg_offset;
>> + priv->reset_reg_num = reg_number;
>> + rst_dev->priv = priv;
>> +
>> + return 0;
>> +}
>> +
>> +U_BOOT_DRIVER(rockchip_reset) = {
>> + .name = "rockchip_reset",
>> + .id = UCLASS_RESET,
>> + .probe = rockchip_reset_probe,
>> + .ops = &rockchip_reset_ops,
>> + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
>> +};
>> --
>> 1.9.1
>>
>
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