[U-Boot] [PATCH v2 2/5] board: TI K2G: FC SoC 1GHz and DDR3 1066 MT/s support
Lokesh Vutla
lokeshvutla at ti.com
Wed Dec 20 15:29:37 UTC 2017
From: Rex Chang <rchang at ti.com>
Added support for K2G EVM with FlipChip SoC of which
ARM/DDR3 runs at 1GHz/1066 MT/s. The patch is also
backward compatible with old revision EVM and EVM
with WireBond SoC. Their ARM/DDR3 run at 600MHz/800 MT/s.
The new SoC supports 2 different speeds at 1GHz and 600MHz.
Modyfied the CPU Name to show which SoC is used in the EVM.
Modified the DDR3 configuration to reflect New SoC supports
2 different CPU and DDR3 speeds, 1GHz/1066MT and 600MHz/800MT.
Added new inline function board_it_k2g_g1() for the new FlipChip 1GHz,
and set the u-boot env variable board_name accordingly.
Modified findfdt script in u-boot environment variable to include new k2g board type.
Signed-off-by: Rex Chang <rchang at ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
arch/arm/mach-keystone/include/mach/hardware.h | 3 ++
arch/arm/mach-keystone/init.c | 17 +++++++-
board/ti/ks2_evm/board.h | 4 ++
board/ti/ks2_evm/board_k2g.c | 32 +++++++++++----
board/ti/ks2_evm/ddr3_k2g.c | 57 +++++++++++++++++++++++++-
board/ti/ks2_evm/mux-k2g.h | 2 +-
include/configs/k2g_evm.h | 4 +-
7 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 6629406870..5d08418eb9 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -327,6 +327,9 @@ typedef volatile unsigned int *dv_reg_p;
#define CPU_66AK2Lx 0xb9a7
#define CPU_66AK2Gx 0xbb06
+/* Variant definitions */
+#define CPU_66AK2G1x 0x08
+
/* DEVSPEED register */
#define DEVSPEED_DEVSPEED_SHIFT 16
#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 6e5a1e1af1..f9c03f1dd1 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -229,7 +229,19 @@ int print_cpuinfo(void)
puts("66AK2Ex SR");
break;
case CPU_66AK2Gx:
- puts("66AK2Gx SR");
+ puts("66AK2Gx");
+#ifdef CONFIG_SOC_K2G
+ {
+ int speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ puts("-100 ");
+ else if (speed == SPD600)
+ puts("-60 ");
+ else
+ puts("-xx ");
+ }
+#endif
+ puts("SR");
break;
default:
puts("Unknown\n");
@@ -241,7 +253,8 @@ int print_cpuinfo(void)
puts("1.1\n");
else if (rev == 0)
puts("1.0\n");
-
+ else if (rev == 8)
+ puts("1.0\n");
return 0;
}
#endif
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index b3ad1881fa..48d60a1c74 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -20,6 +20,10 @@ static inline int board_is_k2g_gp(void)
{
return board_ti_is("66AK2GGP");
}
+static inline int board_is_k2g_g1(void)
+{
+ return board_ti_is("66AK2GG1");
+}
static inline int board_is_k2g_ice(void)
{
return board_ti_is("66AK2GIC");
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 01328f1955..88df419b10 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -55,7 +55,7 @@ unsigned int get_external_clk(u32 clk)
return clk_freq;
}
-static int arm_speeds[DEVSPEED_NUMSPDS] = {
+int speeds[DEVSPEED_NUMSPDS] = {
SPD400,
SPD600,
SPD800,
@@ -159,13 +159,20 @@ static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
};
-static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
+static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
};
+static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
+ [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
+ [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
+ [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
+ [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
+};
+
struct pll_init_data *get_pll_init_data(int pll)
{
int speed;
@@ -178,7 +185,7 @@ struct pll_init_data *get_pll_init_data(int pll)
data = &main_pll_config[sysclk_index][speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed(arm_speeds);
+ speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[sysclk_index][speed];
break;
case NSS_PLL:
@@ -188,7 +195,15 @@ struct pll_init_data *get_pll_init_data(int pll)
data = &uart_pll_config[sysclk_index];
break;
case DDR3_PLL:
- data = &ddr3_pll_config[sysclk_index];
+ if (cpu_revision() & CPU_66AK2G1x) {
+ speed = get_max_arm_speed(speeds);
+ if (speed == SPD1000)
+ data = &ddr3_pll_config_1066[sysclk_index];
+ else
+ data = &ddr3_pll_config_800[sysclk_index];
+ } else {
+ data = &ddr3_pll_config_800[sysclk_index];
+ }
break;
default:
data = NULL;
@@ -209,7 +224,7 @@ int board_mmc_init(bd_t *bis)
return -1;
}
- if (board_is_k2g_gp())
+ if (board_is_k2g_gp() || board_is_k2g_g1())
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
@@ -224,7 +239,8 @@ int board_fit_config_name_match(const char *name)
if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
return 0;
- else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+ else if (!strcmp(name, "keystone-k2g-evm") &&
+ (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
return 0;
else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
return 0;
@@ -283,7 +299,7 @@ int embedded_dtb_select(void)
k2g_reset_mux_config();
- if (board_is_k2g_gp()) {
+ if (board_is_k2g_gp() || board_is_k2g_g1()) {
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
@@ -312,6 +328,8 @@ int board_late_init(void)
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (board_is_k2g_gp())
env_set("board_name", "66AK2GGP\0");
+ else if (board_is_k2g_g1())
+ env_set("board_name", "66AK2GG1\0");
else if (board_is_k2g_ice())
env_set("board_name", "66AK2GIC\0");
#endif
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 44db335580..923401cfd2 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -10,6 +10,7 @@
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
#include "board.h"
/* K2G GP EVM DDR3 Configuration */
@@ -53,6 +54,46 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.pir_v2 = 0x00000F81ul,
};
+struct ddr3_phy_config ddr3phy_1066_2g = {
+ .pllcr = 0x000DC000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0,
+ .ptr3 = 0x0904111Dul,
+ .ptr4 = 0x0859A072ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x6D147744ul,
+ .dtpr1 = 0x32845A80ul,
+ .dtpr2 = 0x50023600ul,
+ .mr0 = 0x00001830ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000000ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F05159ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
+ .pir_v2 = 0x00000F81ul,
+};
+
struct ddr3_emif_config ddr3_800_2g = {
.sdcfg = 0x62005662ul,
.sdtim1 = 0x0A385033ul,
@@ -63,6 +104,16 @@ struct ddr3_emif_config ddr3_800_2g = {
.sdrfc = 0x00000C34ul,
};
+struct ddr3_emif_config ddr3_1066_2g = {
+ .sdcfg = 0x62005662ul,
+ .sdtim1 = 0x0E4C6843ul,
+ .sdtim2 = 0x00001CC6ul,
+ .sdtim3 = 0x323DFF32ul,
+ .sdtim4 = 0x533F08AFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001044ul,
+};
+
/* K2G ICE evm DDR3 Configuration */
struct ddr3_phy_config ddr3phy_800_512mb = {
.pllcr = 0x000DC000ul,
@@ -118,8 +169,10 @@ u32 ddr3_init(void)
{
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
-
- if (board_is_k2g_gp()) {
+ if (board_is_k2g_g1()) {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g);
+ } else if (board_is_k2g_gp()) {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
} else if (board_is_k2g_ice()) {
diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
index 630103d0ff..9e3fa11003 100644
--- a/board/ti/ks2_evm/mux-k2g.h
+++ b/board/ti/ks2_evm/mux-k2g.h
@@ -345,7 +345,7 @@ void k2g_mux_config(void)
{
if (!board_ti_was_eeprom_read()) {
configure_pin_mux(k2g_generic_pin_cfg);
- } else if (board_is_k2g_gp()) {
+ } else if (board_is_k2g_gp() || board_is_k2g_g1()) {
configure_pin_mux(k2g_evm_pin_cfg);
} else if (board_is_k2g_ice()) {
configure_pin_mux(k2g_ice_evm_pin_cfg);
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 9282a22739..4e43104fac 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -34,11 +34,13 @@
"findfdt="\
"if test $board_name = 66AK2GGP; then " \
"setenv name_fdt keystone-k2g-evm.dtb; " \
+ "else if test $board_name = 66AK2GG1; then " \
+ "setenv name_fdt keystone-k2g-evm.dtb; " \
"else if test $board_name = 66AK2GIC; then " \
"setenv name_fdt keystone-k2g-ice.dtb; " \
"else if test $name_fdt = undefined; then " \
"echo WARNING: Could not determine device tree to use;"\
- "fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
+ "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
"name_mon=skern-k2g.bin\0" \
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
--
2.15.1
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