[U-Boot] [RFC PATCH 3/4] sunxi: add initial Allwinner H6 support
Icenowy Zheng
icenowy at aosc.io
Sat Dec 30 15:40:27 UTC 2017
Allwinner H6 is a new SoC in the sun50i series, with Cortex-A53 cores
and refactored memory map/CCU.
Add initial support for it, including initial MMC support.
The offset of the environment is moved to 0xe0000, which used to be the
space reserved for Falcon mode in legacy u-boot-sunxi. This change will
prevent the U-Boot space issue which happened on several sunxi boards.
Signed-off-by: Icenowy Zheng <icenowy at aosc.io>
---
arch/arm/dts/sun50i-h6.dtsi | 140 ++++++++++++
arch/arm/include/asm/arch-sunxi/clock.h | 2 +
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 266 ++++++++++++++++++++++
arch/arm/include/asm/arch-sunxi/cpu.h | 2 +
arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 73 ++++++
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/include/asm/arch-sunxi/mmc.h | 2 +-
arch/arm/include/asm/arch-sunxi/timer.h | 2 +-
arch/arm/mach-sunxi/Kconfig | 7 +
arch/arm/mach-sunxi/Makefile | 3 +-
arch/arm/mach-sunxi/board.c | 6 +-
arch/arm/mach-sunxi/clock_sun50i_h6.c | 39 ++++
arch/arm/mach-sunxi/cpu_info.c | 2 +
board/sunxi/board.c | 2 +-
drivers/mmc/sunxi_mmc.c | 11 +
env/Kconfig | 3 +-
include/configs/sun50i.h | 5 +
include/configs/sunxi-common.h | 5 +-
18 files changed, 564 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/dts/sun50i-h6.dtsi
create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
new file mode 100644
index 0000000000..50f9146318
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy at aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu2: cpu at 2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu3: cpu at 3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-accuracy = <300000000>;
+ clock-output-names = "iosc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller at 3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ uart0: serial at 5000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>; /* placeholder */
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 3747f74d36..ecbef85f83 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -17,6 +17,8 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/clock_sun8i_a83t.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
defined(CONFIG_MACH_SUN50I)
#include <asm/arch/clock_sun6i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
new file mode 100644
index 0000000000..ade576932f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -0,0 +1,266 @@
+/*
+ * Allwinner H6 clock register definitions
+ *
+ * (C) Copyright 2017 Icenowy Zheng <icenowy at aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN50I_H6_H
+#define _SUNXI_CLOCK_SUN50I_H6_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
+ u8 reserved_0x004[12];
+ u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
+ u8 reserved_0x014[12];
+ u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
+ u8 reserved_0x020[4];
+ u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
+ u8 reserved_0x028[4];
+ u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
+ u8 reserved_0x034[12];
+ u32 pll3_cfg; /* 0x040 pll3 (video0) control */
+ u8 reserved_0x044[4];
+ u32 pll_video1_cfg; /* 0x048 pll video1 control */
+ u8 reserved_0x04c[12];
+ u32 pll4_cfg; /* 0x058 pll4 (ve) control */
+ u8 reserved_0x05c[4];
+ u32 pll10_cfg; /* 0x060 pll10 (de) control */
+ u8 reserved_0x064[12];
+ u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
+ u8 reserved_0x074[4];
+ u32 pll2_cfg; /* 0x078 pll2 (audio) control */
+ u8 reserved_0x07c[148];
+ u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
+ u8 reserved_0x114[20];
+ u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */
+ u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */
+ u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
+ u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
+ u8 reserved_0x138[8];
+ u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
+ u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
+ u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */
+ u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */
+ u8 reserved_0x150[8];
+ u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
+ u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
+ u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */
+ u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */
+ u8 reserved_0x168[8];
+ u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
+ u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
+ u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
+ u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
+ u8 reserved_0x180[384];
+ u32 pll1_bias; /* 0x300 pll1 (cpux) bias */
+ u8 reserved_0x304[12];
+ u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
+ u8 reserved_0x314[12];
+ u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
+ u8 reserved_0x324[4];
+ u32 pll_periph1_bias; /* 0x328 pll periph1 bias */
+ u8 reserved_0x32c[4];
+ u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
+ u8 reserved_0x334[12];
+ u32 pll3_bias; /* 0x340 pll3 (video0) bias */
+ u8 reserved_0x344[4];
+ u32 pll_video1_bias; /* 0x348 pll video1 bias */
+ u8 reserved_0x34c[12];
+ u32 pll4_bias; /* 0x358 pll4 (ve) bias */
+ u8 reserved_0x35c[4];
+ u32 pll10_bias; /* 0x360 pll10 (de) bias */
+ u8 reserved_0x364[12];
+ u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
+ u8 reserved_0x374[4];
+ u32 pll2_bias; /* 0x378 pll2 (audio) bias */
+ u8 reserved_0x37c[132];
+ u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */
+ u8 reserved_0x404[252];
+ u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/
+ u8 reserved_0x504[12];
+ u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */
+ u8 reserved_0x514[8];
+ u32 ahb3_cfg; /* 0x51c AHB3 clock control */
+ u32 apb1_cfg; /* 0x520 APB1 clock control */
+ u32 apb2_cfg; /* 0x524 APB2 clock control */
+ u8 reserved_0x528[24];
+ u32 mbus_cfg; /* 0x540 MBUS clock control */
+ u8 reserved_0x544[188];
+ u32 de_clk_cfg; /* 0x600 DE clock control */
+ u8 reserved_0x604[8];
+ u32 de_gate_reset; /* 0x60c DE gate/reset control */
+ u8 reserved_0x610[16];
+ u32 di_clk_cfg; /* 0x620 DI clock control */
+ u8 reserved_0x024[8];
+ u32 di_gate_reset; /* 0x62c DI gate/reset control */
+ u8 reserved_0x630[64];
+ u32 gpu_clk_cfg; /* 0x670 GPU clock control */
+ u8 reserved_0x674[8];
+ u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */
+ u32 ce_clk_cfg; /* 0x680 CE clock control */
+ u8 reserved_0x684[8];
+ u32 ce_gate_reset; /* 0x68c CE gate/reset control */
+ u32 ve_clk_cfg; /* 0x690 VE clock control */
+ u8 reserved_0x694[8];
+ u32 ve_gate_reset; /* 0x69c VE gate/reset control */
+ u8 reserved_0x6a0[16];
+ u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */
+ u8 reserved_0x6b4[8];
+ u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */
+ u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */
+ u8 reserved_0x6c4[8];
+ u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */
+ u8 reserved_0x6d0[60];
+ u32 dma_gate_reset; /* 0x70c DMA gate/reset control */
+ u8 reserved_0x710[12];
+ u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */
+ u8 reserved_0x720[12];
+ u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
+ u8 reserved_0x730[12];
+ u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */
+ u32 avs_gate_reset; /* 0x740 AVS gate/reset control */
+ u8 reserved_0x744[72];
+ u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */
+ u8 reserved_0x790[12];
+ u32 psi_gate_reset; /* 0x79c PSI gate/reset control */
+ u8 reserved_0x7a0[12];
+ u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */
+ u8 reserved_0x7b0[12];
+ u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */
+ u8 reserved_0x7c0[64];
+ u32 dram_clk_cfg; /* 0x800 DRAM clock control */
+ u32 mbus_gate; /* 0x804 MBUS gate control */
+ u8 reserved_0x808[4];
+ u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */
+ u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */
+ u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */
+ u8 reserved_0x818[20];
+ u32 nand_gate_reset; /* 0x82c NAND gate/reset control */
+ u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */
+ u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */
+ u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */
+ u8 reserved_0x83c[16];
+ u32 sd_gate_reset; /* 0x84c MMC gate/reset control */
+ u8 reserved_0x850[188];
+ u32 uart_gate_reset; /* 0x90c UART gate/reset control */
+ u8 reserved_0x910[12];
+ u32 twi_gate_reset; /* 0x91c I2C gate/reset control */
+ u8 reserved_0x920[28];
+ u32 scr_gate_reset; /* 0x93c SCR gate/reset control */
+ u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */
+ u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */
+ u8 reserved_0x948[36];
+ u32 spi_gate_reset; /* 0x96c SPI gate/reset control */
+ u8 reserved_0x970[12];
+ u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */
+ u8 reserved_0x980[48];
+ u32 ts_clk_cfg; /* 0x9b0 TS clock control */
+ u8 reserved_0x9b4[8];
+ u32 ts_gate_reset; /* 0x9bc TS gate/reset control */
+ u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */
+ u8 reserved_0x9c4[8];
+ u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */
+ u8 reserved_0x9d0[44];
+ u32 ths_gate_reset; /* 0x9fc THS gate/reset control */
+ u8 reserved_0xa00[12];
+ u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */
+ u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */
+ u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */
+ u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */
+ u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */
+ u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */
+ u8 reserved_0xa24[8];
+ u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */
+ u8 reserved_0xa30[16];
+ u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */
+ u8 reserved_0xa44[8];
+ u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */
+ u8 reserved_0xa50[16];
+ u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */
+ u8 reserved_0xa64[8];
+ u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */
+ u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */
+ u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */
+ u8 reserved_0xa78[4];
+ u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */
+ u8 reserved_0xa80[12];
+ u32 usb_gate_reset; /* 0xa8c USB gate/reset control */
+ u8 reserved_0xa90[32];
+ u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */
+ u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */
+ u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */
+ u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */
+ u8 reserved_0xac0[64];
+ u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */
+ u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */
+ u8 reserved_0xb08[8];
+ u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */
+ u8 reserved_0xb14[8];
+ u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */
+ u8 reserved_0xb20[60];
+ u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
+ u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */
+ u8 reserved_0xb64[24];
+ u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
+ u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */
+ u8 reserved_0xb84[24];
+ u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */
+ u8 reserved_0xba0[96];
+ u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */
+ u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */
+ u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */
+ u8 reserved_0xc0c[32];
+ u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */
+ u8 reserved_0xc30[16];
+ u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */
+ u8 reserved_0xc44[8];
+ u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */
+ u8 reserved_0xc50[688];
+ u32 ccu_sec_switch; /* 0xf00 CCU security switch */
+ u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */
+};
+
+/* pll6 bit field */
+#define CCM_PLL6_CTRL_N_SHIFT 8
+#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_DIV1_SHIFT 0
+#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
+#define CCM_PLL6_CTRL_DIV2_SHIFT 1
+#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_OSC24M (0x0 << 24)
+#define APB2_CLK_SRC_OSC32K (0x1 << 24)
+#define APB2_CLK_SRC_PSI (0x2 << 24)
+#define APB2_CLK_SRC_PLL6 (0x3 << 24)
+#define APB2_CLK_SRC_MASK (0x3 << 24)
+#define APB2_CLK_RATE_N_1 (0x0 << 8)
+#define APB2_CLK_RATE_N_2 (0x1 << 8)
+#define APB2_CLK_RATE_N_4 (0x2 << 8)
+#define APB2_CLK_RATE_N_8 (0x3 << 8)
+#define APB2_CLK_RATE_N_MASK (3 << 8)
+#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK (3 << 0)
+
+/* Module gate/reset shift*/
+#define RESET_SHIFT (16)
+
+/* MMC clock bit field */
+#define CCM_MMC_CTRL_M(x) ((x) - 1)
+#define CCM_MMC_CTRL_N(x) ((x) << 8)
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24)
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+/* H6 doesn't have these delays */
+#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
+#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll6(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index caec865264..08be963e8e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -9,6 +9,8 @@
#if defined(CONFIG_MACH_SUN9I)
#include <asm/arch/cpu_sun9i.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/cpu_sun50i_h6.h>
#else
#include <asm/arch/cpu_sun4i.h>
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
new file mode 100644
index 0000000000..8421f7637c
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2017 Icenowy Zheng <icenowy at aosc.io>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN50I_H6_H
+#define _SUNXI_CPU_SUN50I_H6_H
+
+#define SUNXI_SRAM_A1_BASE 0x00020000
+#define SUNXI_SRAM_C_BASE 0x00028000
+#define SUNXI_SRAM_A2_BASE 0x00100000
+
+#define SUNXI_DE3_BASE 0x01000000
+#define SUNXI_SS_BASE 0x01904000
+#define SUNXI_EMCE_BASE 0x01905000
+
+#define SUNXI_SRAMC_BASE 0x03000000
+#define SUNXI_CCM_BASE 0x03001000
+#define SUNXI_DMA_BASE 0x03002000
+/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE 0x03006000
+#define SNUXI_SID_BASE 0x03006200
+#define SUNXI_TIMER_BASE 0x03009000
+#define SUNXI_PIO_BASE 0x0300B000
+#define SUNXI_PSI_BASE 0x0300C000
+
+#define SUNXI_GIC400_BASE 0x03020000
+#define SUNXI_IOMMU_BASE 0x030F0000
+
+#define SUNXI_DRAM_COM_BASE 0x04002000
+#define SUNXI_DRAM_CTL0_BASE 0x04003000
+#define SUNXI_DRAM_PHY0_BASE 0x04005000
+#define SUNXI_NFC_BASE 0x04011000
+#define SUNXI_MMC0_BASE 0x04020000
+#define SUNXI_MMC1_BASE 0x04021000
+#define SUNXI_MMC2_BASE 0x04002000
+
+#define SUNXI_UART0_BASE 0x05000000
+#define SUNXI_UART1_BASE 0x05000400
+#define SUNXI_UART2_BASE 0x05000800
+#define SUNXI_UART3_BASE 0x05000C00
+#define SUNXI_TWI0_BASE 0x05002000
+#define SUNXI_TWI1_BASE 0x05002400
+#define SUNXI_TWI2_BASE 0x05002800
+#define SUNXI_TWI3_BASE 0x05002C00
+#define SUNXI_SPI0_BASE 0x05010000
+#define SUNXI_SPI1_BASE 0x05011000
+#define SUNXI_GMAC_BASE 0x05020000
+#define SUNXI_USB0_BASE 0x05100000
+#define SUNXI_XHCI_BASE 0x05200000
+#define SUNXI_USB3_BASE 0x05311000
+#define SUNXI_PCIE_BASE 0x05400000
+
+#define SUNXI_HDMI_BASE 0x06000000
+#define SUNXI_TCON_TOP_BASE 0x06510000
+#define SUNXI_TCON_LCD0_BASE 0x06511000
+#define SUNXI_TCON_TV0_BASE 0x06515000
+
+#define SUNXI_RTC_BASE 0x07000000
+#define SUNXI_R_CPUCFG_BASE 0x07000400
+#define SUNXI_PRCM_BASE 0x07010000
+#define SUNXI_R_PIO_BASE 0x07022000
+#define SUNXI_R_UART_BASE 0x07080000
+#define SUNXI_R_TWI_BASE 0x07081400
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 24f85206c8..5acc3033f5 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -198,6 +198,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2
#define SUN9I_GPH_UART0 2
+#define SUN50I_H6_GPH_UART0 2
#define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 69f737f3bf..4fce9218ff 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -46,7 +46,7 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res2[26];
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u32 res3[64];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index ccdf942534..938067924e 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -77,7 +77,7 @@ struct sunxi_timer_reg {
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index d944e7c015..1513a3294f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -188,6 +188,10 @@ config MACH_SUN50I_H5
select FIT
select SPL_LOAD_FIT
+config MACH_SUN50I_H6
+ bool "sun50i (Allwinner H6)"
+ select ARM64
+
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -403,6 +407,7 @@ config SYS_CLK_FREQ
default 1008000000 if MACH_SUN8I
default 1008000000 if MACH_SUN9I
default 816000000 if MACH_SUN50I
+ default 1320000000 if MACH_SUN50I_H6
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
@@ -412,6 +417,7 @@ config SYS_CONFIG_NAME
default "sun8i" if MACH_SUN8I
default "sun9i" if MACH_SUN9I
default "sun50i" if MACH_SUN50I
+ default "sun50i" if MACH_SUN50I_H6
config SYS_BOARD
default "sunxi"
@@ -617,6 +623,7 @@ config VIDEO_SUNXI
depends on !MACH_SUN8I_V3S
depends on !MACH_SUN9I
depends on !MACH_SUN50I
+ depends on !MACH_SUN50I_H6
select VIDEO
imply VIDEO_DT_SIMPLEFB
default y
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 2a3c379b72..3fe68e083b 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -13,7 +13,7 @@ obj-y += clock.o
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
-ifndef CONFIG_MACH_SUN9I
+ifeq ($(CONFIG_MACH_SUN9I)$(CONFIG_MACH_SUN50I_H6),)
obj-y += usb_phy.o
endif
obj-$(CONFIG_MACH_SUN6I) += prcm.o
@@ -33,6 +33,7 @@ else
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
+obj-$(CONFIG_MACH_SUN50I_H6) += clock_sun50i_h6.o
obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 0c60ee04da..dcdc430d3d 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -108,6 +108,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
@@ -293,7 +297,7 @@ void reset_cpu(ulong addr)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
new file mode 100644
index 0000000000..152fcee255
--- /dev/null
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -0,0 +1,39 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* uart clock source is apb2 */
+ writel(APB2_CLK_SRC_OSC24M|
+ APB2_CLK_RATE_N_1|
+ APB2_CLK_RATE_M(1),
+ &ccm->apb2_cfg);
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->uart_gate_reset,
+ 1 << (CONFIG_CONS_INDEX - 1));
+
+ /* deassert uart reset */
+ setbits_le32(&ccm->uart_gate_reset,
+ 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
+}
+
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ uint32_t rval = readl(&ccm->pll6_cfg);
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+ int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+ CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+ int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
+ CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+ /* The register defines PLL6-4X, not plain PLL6 */
+ return 24000000 * n / div1 / div2 / 4;
+}
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 25a5ec26a0..90aff395dc 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -97,6 +97,8 @@ int print_cpuinfo(void)
puts("CPU: Allwinner A64 (SUN50I)\n");
#elif defined CONFIG_MACH_SUN50I_H5
puts("CPU: Allwinner H5 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN50I_H6
+ puts("CPU: Allwinner H6 (SUN50I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index dcacdf3e62..3a85087d9a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -729,7 +729,7 @@ int misc_init_r(void)
setup_environment(gd->fdt_blob);
-#ifndef CONFIG_MACH_SUN9I
+#if !defined(CONFIG_MACH_SUN9I) && !defined(CONFIG_MACH_SUN50I_H6)
ret = sunxi_usb_phy_probe();
if (ret)
return ret;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4edb4be46c..e176bdcaa9 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no)
priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
priv->mclkreg = &ccm->sd2_clk_cfg;
break;
+#ifdef SUNXI_MMC3_BASE
case 3:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
priv->mclkreg = &ccm->sd3_clk_cfg;
break;
+#endif
default:
printf("Wrong mmc number %d\n", sdc_no);
return -1;
@@ -116,6 +118,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
#ifdef CONFIG_MACH_SUN9I
pll = CCM_MMC_CTRL_PLL_PERIPH0;
pll_hz = clock_get_pll4_periph0();
+#elif defined(CONFIG_MACH_SUN50I_H6)
+ pll = CCM_MMC_CTRL_PLL6X2;
+ pll_hz = clock_get_pll6() * 2;
#else
pll = CCM_MMC_CTRL_PLL6;
pll_hz = clock_get_pll6();
@@ -504,6 +509,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
/* config ahb clock */
debug("init mmc %d clock and io\n", sdc_no);
+#if !defined(CONFIG_MACH_SUN50I_H6)
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
#ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -514,6 +520,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
/* sun9i has a mmc-common module, also set the gate and reset there */
writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
+#else /* CONFIG_MACH_SUN50I_H6 */
+ setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
+ /* unassert reset */
+ setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
#endif
ret = mmc_set_mod_clk(priv, 24000000);
if (ret)
diff --git a/env/Kconfig b/env/Kconfig
index 8c9d800f48..8fae66de90 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -410,7 +410,8 @@ config ENV_OFFSET
hex "Environment Offset"
depends on !ENV_IS_IN_UBI
depends on !ENV_IS_NOWHERE
- default 0x88000 if ARCH_SUNXI
+ default 0x88000 if ARCH_SUNXI && !MACH_SUN50I_H6
+ default 0xe0000 if MACH_SUN50I_H6
help
Offset from the start of the device (or partition)
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
index b7b67a1ddc..1b3e84c4e9 100644
--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -18,8 +18,13 @@
#define CONFIG_SUNXI_USB_PHYS 1
+#ifndef CONFIG_MACH_SUN50I_H6
#define GICD_BASE 0x1c81000
#define GICC_BASE 0x1c82000
+#else
+#define GICD_BASE 0x3021000
+#define GICC_BASE 0x3022000
+#endif
/*
* Include common sunxi configuration where most the settings are
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 4391a8cbc8..214e1a49ac 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -32,7 +32,7 @@
# define CONFIG_MACH_TYPE_COMPAT_REV 1
#endif
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUN50I_H6)
#define CONFIG_BUILD_TARGET "u-boot.itb"
#endif
@@ -98,6 +98,9 @@
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x08000
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
--
2.14.2
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